Features

10.1 Introduction

This chapter describes the Serial Peripheral Interface (SPI) module. The module allows full-duplex, synchronous, serial communication between the controller and peripheral devices, including other controllers. Software can poll SPI status flags or SPI operation can be interrupt driven. This block contains four 16-bit memory mapped registers for control parameters, status, and data transfer.

10.2 Features

Features of the SPI module include:

•Full-duplex operation

•Master and slave modes

•Double-buffered operation with separate transmit and receive registers

•Programmable length transmissions (2 to 16 bits)

•Programmable transmit and receive shift order (MSB first or last bit transmitted)

•Eight master mode frequencies (maximum = bus frequency 2)

•Maximum slave mode frequency = bus frequency

•Clock ground for reduced radio frequency (RF) interference

•Serial clock with programmable polarity and phase

•Two separately enabled interrupts

—SPRF (SPI Receiver Full)

—SPTE (SPI Transmitter Empty)

•Mode fault error flag interrupt capability

•Wired OR mode functionality to enabling connection to multiple SPIs

Signal Descriptions

Slave output data on the MISO pin is enabled only when the SPI is configured as a slave. The SPI is configured as a slave when the SPMSTR bit, illustrated in Figure 10-13, is Logic 0 and its SS pin is at Logic 0. To support a multiple slave system, a Logic 0 on the SS pin puts the MISO pin in a High-Z state.

10.4.2 Master Out/Slave In (MOSI)

MOSI is the other SPI module pin dedicated to transmit serial data. In full duplex operation, the MOSI pin of the master SPI module is connected to the MOSI pin of the slave SPI module. The master SPI simultaneously transmits data from its MOSI pin and receives data on its MISO pin.

10.4.3 Serial Clock (SCLK)

The serial clock synchronizes data transmission between master and slave devices. In a master controller, the SCLK pin is the clock output. In a slave controller, the SCLK pin is the clock input. In full duplex operation, the master and slave controller exchange data in the same number of clock cycles as the number of bits of transmitted data.

10.4.4 Slave Select (SS)

The SS pin has various functions depending on the current state of the SPI. For an SPI configured as a slave, the SS is used to select a slave. When the Clock Phase (CPHA) bit in the SPSCR is cleared, the SS is used to define the start of a transmission, so it must be toggled high and low between each full length data transmitted for the CPHA = 0 format. However, it can remain low between transmissions for the CPHA = 1 format as illustrated in Figure 10-2.

Figure 10-2. CPHA/SS Timing

When an SPI is configured as a slave, the SS pin is always configured as an input. The MODFEN bit can prevent the state of the SS from creating a MODF error.

Note: A Logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high impedance state. The slave SPI ignores all incoming SCLK clocks, even if it was already in the middle of a transmission. A mode fault occurs if the SS pin changes state during a transmission.

External I/O Signals

When an SPI is configured as a master, the SS input can be used in conjunction with the MODF flag to prevent multiple masters from driving MOSI and SCLK. For the state of the SS pin to set the MODF flag, the MODFEN bit in the SCLK register must be set.

Table 10-1. SPI I/O Configuration

X = Don’t care

10.5 External I/O Signals

There are four external SPI pins. Each is summarized in Table 10-2.

Table 10-2. External I/O Signals

10.6 Operating Modes

The SPI has two operating modes:

1.Master

2.Slave

An operating mode is selected by the SPMSTR bit in the SPSCR as follows:

•SPMSTR = 0 Slave mode

•SPMSTR = 1 Master mode

Note: The SPMSTR bit should be configured before enabling the SPI, setting the SPE bit in the SPSCR. The master SPI should be enabled before enabling any slave SPI. All slave SPIs should be disabled before disabling the master SPI.

Operating Modes

10.6.1 Master Mode

The SPI operates in Master mode when the SPI master bit, SPMSTR, is set.

Note: Configure the SPI module as master or slave before enabling the SPI. Enable the master SPI before enabling the slave SPI. Disable the slave SPI before disabling the master SPI.

Only a Master SPI module can initiate transmissions. With the SPI enabled, software begins the transmission from the master SPI module by writing to the SPI Data Transmit Register (SPDTR). If the Shift Register is empty, the data immediately transfers to the Shift Register, setting the SPI Transmitter Empty (SPTE) bit. The data begins shifting out on the MOSI pin under the control of the SPI Serial Clock (SCLK).

The SPR1 and SPR0 bits in the SPSCR control the baud rate generator and determine the speed of the Shift Register. The baud rate generator of the master also controls the Shift Register of the slave peripheral via the SCLK pin.

As the data shifts out on the MOSI pin of the master, external data shifts in from the slave on the master’s MISO pin. The transmission ends when the SPI Receiver Full (SPRF) bit in the SPSCR becomes set. At the same time the SPRF becomes set, the data from the slave transfers to the SPI Data Receive Register (SPDRR). In a normal operation, SPRF signals the end of a transmission. Software clears the SPRF by reading the SPSCR register with SPRF set and then reading the SPI Data Receive register, SPDRR. Writing to the SPI Data Transmit register, SPDTR, clears the SPTE bit.

Figure 10-3 is an example configuration for a Full-Duplex Master-Slave Configuration. Having the SS bit of the Master controller held high is only necessary if MODFEN = 1. Tying the Slave controller SS bit to ground should only be executed if CPHA = 1.

Figure 10-3. Full-Duplex Master/Slave Connections

Operating Modes

10.6.2 Slave Mode

The SPI operates in the Slave mode when the SPMSTR bit is cleared. While in the Slave mode, the SCLK pin acts as the input for the serial clock from the master controller. Before a data transmission occurs, the SS pin of the slave SPI must be at Logic 0. SS must remain low until the transmission is complete or a Mode Fault error occurs.

Note: The SPI must be enabled (SPE = 1) for slave transmissions to be received.

Note: Data in the transmitter Shift Register will be unaffected by SCLK transitions in the event the SPI is operating as a slave but is deselected.

In a slave SPI module, data enters the Shift Register under the control of the serial clock, SCLK, from the master SPI module. After a full length data transmission enters the Shift Register of a slave SPI, it transfers to the SPDRR and the SPRF bit in the SPSCR is set. If the Receive Interrupt Enable (SPRIE) bit in the SPSCR has been set, a receive interrupt is also generated. To prevent an overflow condition, slave software must read the SPDRR before another full length data transmission enters the Shift Register.

The maximum frequency of the SCLK for an SPI configured as a slave is the bus clock speed. The bus clock speed is twice as fast as the fastest master SCLK potential generation. Frequency of the SCLK for an SPI configured as a slave does not have to correspond to any particular SPI baud rate. The baud rate only controls the speed of the SCLK generated by an SPI configured as a master. Therefore, the frequency of the SCLK for an SPI configured as a slave can be any frequency less than or equal to the bus speed.

When the master SPI starts a transmission, the data in the slave Shift Register begins shifting out on the MISO pin. The slave can load its Shift Register with new data for the next transmission by writing to its Transmit Data Register. The slave must write to its Transmit Data Register at least one bus cycle before the master starts the next transmission. Otherwise, the data already in the slave Shift Register shifts out on the MISO pin. Data written to the slave Shift Register during a transmission remains in a buffer until the end of the transmission.

When the CPHA bit is set, the first edge of SCLK starts a transmission. When CPHA is cleared, the falling edge of SS starts a transmission.

Note: SCLK must be in the proper idle state before the slave is enabled to prevent SCLK from appearing as a clock edge.