Features

9.1 Introduction

This chapter describes the Serial Communications Interface (SCI) module. The module allows asynchronous serial communications with peripheral devices and other controllers.

9.2Features

•Full-duplex or single wire operation

•Standard mark/space Non-Return-to-Zero (NRZ) format

•Thirteen-bit baud rate selection

•Programmable 8-bit or 9-bit data format

•Separately enabled transmitter and receiver

•Separate receiver and transmitter CPU interrupt requests

•Programmable polarity for transmitter and receiver

•Two receiver wake up methods:

—Idle line

—Address mark

•Interrupt-driven operation with seven flags:

—Transmitter empty

—Transmitter idle

—Receiver full

—Receiver overrun

—Noise error

—Framing error

—Parity error

•Receiver framing error detection

•Hardware parity checking

•1/16 bit-time noise detection

Block Diagram

9.3 Block Diagram

SCI Data

Register

TXD

PIN

Figure 9-1. SCI Block Diagram

9.4 Signal Descriptions

9.4.1 Transmit Data (TXD) Pin

The Transmit Data Pin (TXD) is the SCI transmitter pin. TXD is available for generalpurpose I/O when it is not configured for transmitter operation (TE = 0).

9.4.2 Receiver Data (RXD) Pin

The Receiver Data Pin (RXD) is the SCI receiver pin. RXD is available for general-purpose I/O when it is not configured for receiver operation (RE = 0).

The data in Table 9-1 are external I/O signals for the chip interface.

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Functional Description

Table 9-1. External I/O Signals

9.5 Functional Description

Figure 9-1explains the structure of the SCI module. The SCI allows full duplex, asynchronous, NRZ serial communication between the controller and remote devices, including other controllers. The SCI transmitter and receiver operate independently, although they use the same baud rate generator. The controller monitors the status of the SCI, writes the data to be transmitted, and processes received data.

When initializing the SCI, be sure to set the proper peripheral enable bits in the GPIO registers as well as any pull-up enables.

9.5.1 Data Frame Format

The SCI uses the standard Non-Return-to-Zero (NRZ) mark/space data frame format illustrated in Figure 9-2.

Figure 9-2. SCI Data Frame Formats

Each data character is contained in a frame including a Start bit, eight or nine Data bits, and a Stop bit. Clearing the M bit in the SCI Control Register (SCICR) configures the SCI for 8-bit data characters. A frame with eight Data bits has a total of 10 bits.

Table 9-2. Example 8-Bit Data Frame Formats

1.The address bit identifies the frame as an address character. Please see Section 9.5.4.8, Receiver Wake Up

Functional Description

Setting the M bit configures the SCI for 9-bit data characters. A frame with nine Data bits has a total of 11 bits.

Table 9-3. Example 9-Bit Data Frame Formats

1.The address bit identifies the frame as an address character. Please see Section 9.5.4.8, Receiver Wake Up

9.5.2Baud Rate Generation

A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the transmitter. A value of one to 8191 written to the SBR bits determines the module clock divisor. A value of 0 disables the baud rate generator. The SBR bits are bits 12:0 of the SCI Baud Rate (SCIBR) register. The baud rate clock is synchronized with the bus clock, driving the receiver. The baud rate clock, divided by 16, drives the transmitter. The receiver has an acquisition rate of 16 samples per bit time.

Baud rate generation is subject to two sources of error:

1.Integer division of the module clock may not give the exact target frequency.

2.Synchronization with the bus clock can cause phase shift.

Table 9-4 lists examples of achieving target baud rates with a module clock frequency of 60MHz.

Table 9-4. Example Baud Rates (Module Clock = 60Mhz)

Functional Description

To initiate a SCI transmission:

1.Enable the transmitter by writing a Logic 1 to the Transmitter Enable (TE) bit in the SCI Control Register (SCICR).

2.Clear the Transmit Data Register Empty (TDRE) flag by first reading the SCI Status Register (SCISR) and then writing to the SCI Data Register (SCIDR).

3.Repeat step two above for each subsequent transmission.

Modifying the TE bit from zero to a one automatically loads the Transmit Shift Register with a preamble of 10 Logic 1s (if M = 0) or 11 Logic 1s (if M = 1). After the preamble shifts out, control logic automatically transfers the data from the SCI Data Register into the Transmit Shift Register. A Logic 0 Start bit automatically goes into the least significant bit position of the Transmit Shift Register. A Logic 1 Stop bit goes into the Most Significant Bit (MSB) position of the frame.

Hardware supports odd or even parity. When parity is enabled, the MSB of the data character is replaced by the parity bit.

The Transmit Data Register Empty (TDRE) flag in the SCI Status Register (SCISR) becomes set when the SCI Data Register transfers a character to the Transmit Shift Register. The TDRE flag indicates when the SCI Data Register can accept new data from the internal data bus. If the Transmitter Empty Interrupt Enable (TEIE) bit in the SCI Control Register (SCICR) is also set, the TDRE flag generates a transmitter interrupt request.

When the Transmit Shift Register is not transmitting a frame and TE = 1, the TXD pin goes to the idle condition, Logic 1. If at any time software clears the TE bit in the SCI Control Register (SCICR), the transmitter relinquishes control of the port I/O pin upon completion of the current transmission causing the TXD pin to go to a HighZ state.

If software clears TE while a transmission is in progress (TIDLE = 0), the frame in the Transmit Shift Register continues to shift out. Then transmission stops even if there is data pending in the SCI Data Register. To avoid accidentally cutting off the last frame in a message, always wait for TDRE to go high after the last frame before clearing TE.

To separate messages with preambles with minimum idle line time, use this sequence between messages:

1.Write the last character of the first message to SCIDR.

2.Wait for the TDRE flag to go high, indicating the transfer of the last frame to the Transmit Shift Register.

3.Queue a preamble by clearing and then setting the TE bit.

4.Write the first character of the second message to SCIDR.

Functional Description

9.5.3.3 Break Characters

Writing Logic 1 to the Send Break (SBK) bit in the SCI Control Register (SCICR) loads the Transmit Shift Register with a break character. A break character contains all logic zeros and has no Start, Stop, or Parity bit. Break character length depends on the M bit in the SCI Control Register (SCICR). As long as SBK is at Logic 1, transmitter logic continuously loads break characters into the Transmit Shift Register. After software clears the SBK bit, the Shift register finishes transmitting the last break character and then transmits at least one Logic 1. The automatic Logic 1 at the end of the last break character guarantees the recognition of the Start bit of the next frame.

The SCI recognizes a break character when a start bit is followed by eight or nine logic zero data bits and a logic zero where the Stop bit should be. Receiving a break character has these effects on SCI registers:

•Sets the Framing Error flag (FE)

•Sets the Receive Data Register Full flag (RDRF)

•Clears the SCI Data Register (SCIDR)

•May set the Overrun (OR) flag, Noise Flag (NF), Parity Error (PE) flag, or the Receiver Active Flag (RAF). Please see the SCI Status Register in Section 9.8.3.

9.5.3.4 Preambles

A preamble contains all logic ones and has no Start, Stop, or Parity bit. A preamble length depends on the M bit in the SCI Control Register (SCICR). The preamble is a synchronizing mechanism that begins the first transmission initiated after modifying the TE bit from zero to one.

If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the transmission in progress. Clearing and then setting the TE bit during a transmission queues a preamble to be sent after the frame currently being transmitted.

Note: Toggle the TE bit for a queued preamble when the TDRE flag becomes set and immediately before writing the next character to the SCI Data Register.

When queueing a preamble, return the TE bit to Logic 1 before the Stop bit of the current frame shifts out to the TXD pin. Setting TE after the Stop bit appears on TXD causes data previously written to the SCI Data Register to be lost.

9.5.3.5 Receiver

Figure 9-4 explains the block diagram of the SCI receiver with detailed discussion of the receiver function in the following paragraphs.

Functional Description

9.5.4 Receiver Block Diagram

INTERNAL BUS

Figure 9-4. SCI Receiver Block Diagram

9.5.4.1 Character Length

The SCI receiver can accommodate either 8- or 9-bit data characters. The state of the M bit in the SCI Control Register (SCICR) determines the length of data characters.

9.5.4.2 Character Reception

During an SCI reception, the Receive Shift Register shifts a frame in from the RXD pin. The data is read from the SCI Data Register (SCIDR).

After a complete frame shifts into the Receive Shift Register, the data portion of the frame transfers to the SCI Data Register. The Receive Data Register Full (RDRF) flag in the SCI Status Register (SCISR) becomes set, indicating the received character can be read. If the Receive Full Interrupt Enable (RFIE) bit in the SCI Control Register (SCICR) is also set, the RDRF flag generates an RDRF interrupt request.

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Functional Description

9.5.4.3 Data Sampling

The receiver samples the RXD pin at the RT clock rate. The RT clock is an internal signal with a frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock illustrated in Figure 9-5 is resynchronized:

•After every start bit

•After the receiver detects a data bit change from Logic 1 to Logic 0 (after the majority of data bit samples at RT8, RT9, and RT10 returns a valid Logic 1 and the majority of the next RT8, RT9, and RT10 samples returns a valid Logic 0)

To locate the start bit, data recovery logic does an asynchronous search for a Logic 0 preceded by three logic ones. When the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

RESET RT CLOCK

Figure 9-5. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7. Table 9-5 summarizes the results of the Start bit verification samples. If the start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

Table 9-5. Start Bit Verification

Functional Description

If start bit verification is not successful, the RT clock is reset and a new search for a start bit begins.

To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 9-6 summarizes the results of the data bit samples.

Table 9-6. Data Bit Recovery

Note: The RT8, RT9, and RT10 samples do not affect start bit verification. If any or all of the RT8, RT9, and RT10 Start bit samples are logic ones following a successful start bit verification, the Noise Flag (NF) is set and the receiver assumes that the bit is a Start bit (Logic 0).

To verify a Stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 9-7 summarizes the results of the Stop bit samples.

Table 9-7. Stop Bit Recovery

Figure 9-6 illustrates the verification samples RT3 and RT5 determine the first low detected was noise and not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag is not set because the noise occurred before the start bit was found.

Functional Description

START BIT LSB

RESET RT CLOCK

Figure 9-6. Start Bit Search Example 1

Figure 9-7 shows noise is perceived as the beginning of a start bit although the verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.