Resets

8.10 Resets

8.10.1 Reset Handshake Timing

The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RST is asserted. The reset vector will be presented until the second rising clock edge after RST is released. The general timing is illustrated in the following diagram.

8.10.2 ITCN After Reset

After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except the core IRQs with fixed priorities. Those core IRQs are:

•Illegal Instruction

•SW Interrupt 3

•HW stack overflow

•Misaligned long word access

•SW Interrupt 2

•SW Interrupt 1

•SW Interrupt 0

•SW Interrupt LP

These exceptions are enabled at their fixed priority levels.

8.11 Interrupts

8.11.1 Interrupt Handshake Timing

The control logic looks at the current interrupt processing level using the SR_REG[9:8] bits from the 56800E core and determines if an interrupt request of sufficient priority exists to assert the interrupt output to the core. Please see Figure 8-24. Upon asserting INT to the core, the interrupt controller also asserts new values for the IPIC_LEVEL pins. These pins indicate the priority level

Interrupts

required to interrupt this newly requested interrupt. The core will latch IPIC_LEVEL and it will be driven back to the interrupt controller as new values on the SR_REG[9:8] pins.

When the core recognizes the assertion of the interrupt pin, it will deassert PIC_EN. This tells the Interrupt Controller to drive VAB with the address corresponding to the highest priority interrupt request in order to start the interrupt service routine. When the core asserts the IACK signal, the Interrupt Controller will deassert the interrupt signal to the core. The controller will not reassert the interrupt signal until PIC_EN is asserted by the 56800E core.

Figure 8-24. Interrupt Handshake Timing

8.11.2 Interrupt Nesting

Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be serviced. The following two tables define the nesting requirements for each priority level.

Table 8-4. Interrupt Mask Bit Definition

Interrupts

Table 8-5. Interrupt Priority Encoding

Chapter 9

Serial Communications Interface (SCI)