Register Descriptions (COP_BASE = $1FFFD0)

7.9 Register Descriptions (COP_BASE = $1FFFD0)

7.9.1 COP Control Register (COPCTL)

Figure 7-3. COP Control Register (COPCTL)

See Programmer’s Sheet on Appendix page B-18

7.9.1.1 Reserved—Bits 15–5

This bit field is reserved or not implemented. Each bit in the field is read as 0 and cannot be modified by writing.

7.9.1.2 Bypass (BYPS)—Bit 4

This bit is intended for factory use only. Setting this bit allows testing time of the COP to be accelerated by routing the IPBus clock to the counter instead of the OSCCLK. This bit should not be set during normal operation of the chip. If this bit is used, however, it should only be changed while the CEN bit is set to 0.

•0 = Counter uses OSCCLK (default)

•1 = Counter uses IPBus clock

7.9.1.3 COP Stop Mode Enable (CSEN)—Bit 3

This bit controls the operation of the COP counter in the Stop mode. This bit can only be changed when the CWP bit is set to 0.

•0 = COP counter will stop in the Stop mode (default)

•1 = COP counter will run in the Stop mode if CEN is set to 1

7.9.1.4 COP Wait Mode Enable (CWEN)—Bit 2

This bit controls the operation of the COP counter in the Wait mode. This bit can only be changed when the CWP bit is set to 0.

•0 = COP counter will stop in the Wait mode (default)

•1 = COP counter will run in the Wait mode if CEN is set to 1

Register Descriptions (COP_BASE = $1FFFD0)

7.9.1.5 COP Enable (CEN)—Bit 1

This bit controls the operation of the COP counter. This bit can only be changed when the CWP bit is set to 0. This bit always reads as 0 when the chip is in the Debug mode.

•0 = COP counter is disabled (default)

•1 = COP counter is enabled

7.9.1.6 COP Write Protect (CWP)—Bit 0

This bit controls the write protection feature of the COP Control (COPCTL) register and the COP Time-Out (COPTO) register. Once set, this bit can only be cleared by resetting the module.

•0 = COPCTL and COPTO are readable and writable (default)

•1 = COPCTL and COPTO are read only

7.9.2 COP Time-Out Register (COPTO)

Figure 7-4. COP Time-Out Register (COPTO)

See Programmer’s Sheet on Appendix page B-19

7.9.2.1 COP Time-Out Period (TIMEOUT)—Bits 15–0

The value in this register determines the time-out period of the COP counter. TIMEOUT should be written before the COP is enabled. Once the COP is enabled, the recommended procedure for changing TIMEOUT is to disable the COP, write to COPTO, then re-enable the COP, ensuring the new TIMEOUT is loaded into the counter. Alternatively, the CPU can write to COPTO, then write the proper patterns to COPCTR, causing the counter to reload with the new TIMEOUT value. The COP counter is not reset by a write to COPTO. Changing TIMEOUT while the COP is enabled will result in a time-out period differing from the expected value. These bits can only be changed when the CWP bit is set to 0.

Power-On Reset (POR) and Computer Operating Properly (COP), Rev. 4

Clocks

7.9.3 COP Counter Register (COPCTR)

Figure 7-5. COP Counter Register (COPCTR)

See Programmer’s Sheet on Appendix page B-20

7.9.3.1 COP Count (COUNT)—Bits 15–0

This is the current value of the COP counter as it counts down from the time-out value to zero. A reset is issued when this count reaches zero.

7.9.3.2 COP Service (SERVICE)—Bits 15–0

When enabled, the COP requires a service sequence be performed periodically in order to clear the COP counter and prevent a reset from being issued. This routine consists of writing $5555 to the COPCTR followed by writing $AAAA before the time-out period expires. The writes to COPCTR must be performed in the correct order, but any number of other instructions, and writes to other registers, may be executed between the two writes.

7.10 Clocks

The COP timer base is the oscillator clock divided by a fixed prescalar value. The prescalar divisor for this chip is 128.

7.11 Resets

Any system reset forces all registers to their reset state, clearing the COP_RST signal when it is asserted. The counter will be loaded with its maximum value of $FFFF, but it will not start when Reset is released because the CEN bit is disabled by default.

7.12 Interrupts

The COP module does not generate any interrupts. It does generate the COP_RST signal when the counter reaches a value of $0000, causing a chip wide reset.

Chapter 8

Interrupt Controller (ITCN)