Introduction

1.1 Introduction

This manual describes the 56852 device. The design of the 56852 is based on the 56800E core architecture, providing more processing power than any other controller. A primary advantage of the 56852 is it can be used to support microcontroller functions ordinarily requiring a separate microcontroller. This saves designers both space and money.

The 56852 is a member of the 56800E core-based family of Digital Signal Controllers (DSCs). On a single chip, it combines the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56852 is well-suited for many applications. The chip includes many peripherals especially useful for low-end Internet appliance applications and low-end client applications such as:

•Telephony

•Portable devices

•Internet audio

•Point-of-sale systems such as noise suppression

•ID tag readers

•Sonic/subsonic detectors

•Security access devices

•Remote metering

•Sonic alarms

The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming model and optimized instruction set allow straightforward generation of efficient, compact code for both DSP and MCU applications. The instruction set is also highly efficient for C Compilers, enabling rapid development of optimized control applications.

The 56852 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56852 also provides two external dedicated interrupt lines, and up to 11 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration.

The 56852 controller includes 6K words of Program RAM, 4K words of Data RAM and 1K of Boot ROM. This controller also provides a full set of standard programmable peripherals including one Improved Synchronous Serial Interface (ISSI), or one Serial Peripheral Interface (SPI), one improved Serial Communications Interface (SCI), and one Quad Timer (TMR). The

56800E Core Description

ISSI, SPI, SCI I/O and three chip selects can be used as General Purpose Input/Outputs (GPIOs) when its primary function is not required. The ISSI and SPI share I/O. At most, one of these two peripherals can be in use at any time.

1.2 56800E Core Description

This section provides a brief overview of the 56800E core. For a more thorough description refer to the 56800E Reference Manual (DSP56800ERM).

1.2.1 Key Features

The 56800E architecture provides a variety of features to enhance performance, reduce application cost, and ease product development. The architectural features making these benefits possible include:

•Efficient 16-bit engine with dual Harvard architecture

•120 Million Instructions Per Second (MIPS) at 120MHz core frequency

•Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

•Four 36-bit accumulators including extension bits

•16-bit bidirectional shifter

•Parallel instruction set with unique addressing modes

•Hardware DO and REP loops

•Three internal address buses and one external address bus

•Four internal data buses and one external data bus

•Instruction set supports both DSP and controller functions

•Four hardware interrupt levels

•Five software interrupt levels

•Controller-style addressing modes and instructions for compact code

•Efficient C Compiler and local variable support

•Software sub routine and interrupt stack with depth limited only by memory

•JTAG/Enhanced OnCE™ debug programming interface

1.2.2 56800E Core Enhancements

The 56800E core architecture extends the 56800 family architecture. It is source-code compatible with 56800devices, adding these new features:

•Byte and long data types, supplementing the 56800’s word data type

56800E Core Description

•24-bit data memory address space

•21-bit program memory address space

•Two additional 24-bit pointer registers

•Two additional 36-bit accumulator registers

•Full-precision integer multiplication

•32-bit logical and shifting operations

•Second read in dual read instruction can access off-chip memory

•Loop Count (LC) register extended to 16 bits

•Support for nested DO looping through additional loop address and count registers

•Loop address and hardware stack extended to 24 bits

•Three additional interrupt levels with a software interrupt for each level

•Enhanced On-Chip Emulation (EOnCE) with three debugging modes:

—non-intrusive real-time debugging

—minimally intrusive real-time debugging

—breakpoint and step mode (core is halted)

1.2.3 System Architecture and Peripheral Interface

The 56800E system architecture encompasses all the on-chip components, including the core, on-chip memory, peripherals, and the buses necessary to connect them. Figure 1-1 shows the overall system architecture for a device with an external bus.

56800E Core Description

Figure 1-1. 56800E Chip Architecture with External Bus

The complete architecture includes the following components:

•56800E core

•On-chip program memory

•On-chip data memory

•On-chip peripherals

•IPBus peripheral interface

•External bus interface

Some 56800E devices might not implement an external bus interface. Regardless of the implementation, all peripherals communicate with the 56800E core via the IPBus interface. The IPBus interface standard connects the two data address buses and the CDBR, CDBW, and XDB2 unidirectional data buses to the corresponding bus interfaces on the peripheral devices. The program memory buses are not connected to peripherals.

56852 Digital Signal Controller User Manual, Rev. 4

56800E Core Description

1.2.4 56800E Core Block Diagram

The 56800E core is composed of several independent functional units. The program controller, Address Generation Unit (AGU), and data Arithmetic Logic Unit (ALU) contain their own register sets and control logic, allowing them to operate independently and in parallel, increasing throughput. There is also an independent bit-manipulation unit, enabling efficient bit-manipulation operations. Each functional unit interfaces with the other units, memory, and the memory-mapped peripherals over the core’s internal address and data buses. A block diagram of the 56800E core architecture is shown in Figure 1-2.