Block Diagram

7.3 Block Diagram

Analog Power

GND

Figure 7-1. POR Module Block Diagram

7.4 Method of Operation

Starting with the chip unpowered, the analog and digital power supplies turned on, the bandgap voltage reference and the comparators will begin to function. The bandgap voltage reference will apply a temperature and supply stable voltage reference to the positive inputs of the comparators. Negative inputs of the comparators are connected to voltage points that move proportionately with respect to the analog and digital power supplies.

Initially, the bandgap voltage reference point is greater than the power supply reference signals and the output of the comparators is high. As each power supply goes above it’s trip point, the voltage on the respective comparators negative input will become higher in value than the bandgap voltage reference voltage on the positive input to the comparator and the output of the comparator will go low. If either power supply drops below the trip point the respective POR output will again go high.

For the analog power supply, the POR trip point is:

Computer Operating Properly (COP) Module

For the digital power supply the POR trip point is:

This means, as long as the analog power supply is below 2.8V, the POR_3p3 will be high. When the analog power supply exceeds 2.9V the POR_3p3 output will be low. Respectively, for the digital power supply, when the digital power supply is below 1.62V the POR_1p8 output will be high. When the digital power supply is above 1.7V the POR_1p8 output will be low.

7.5 Computer Operating Properly (COP) Module

The Computer Operating Properly (COP) module is used to help software recover from runaway code. The COP is a free-running down counter, once enabled is designed to generate a Reset upon reaching zero. Software must periodically service the COP in order to clear the counter and prevent a reset.

7.5.1 COP Functional Description

When the COP is enabled, each positive edge of OSCCLK will cause the counter to decrement by one. If the count reaches a value of $0000, then the COP_RST signal is asserted and the chip is reset. In order for the CPU to show it is operating properly, it must perform a service routine prior to the count reaching $0000. The service routine consists of writing $5555 followed by $AAAA to COPCTR.

7.5.2 Time-Out Specifications

The COP uses a 16-bit counter, being clocked by the crystal oscillator clock prescaled by 128. Table 7-1 presents the range of time-out values supported as a function of oscillator frequency.

Table 7-1. COP Time-Out Ranges as a Function of Oscillator Frequency

For a crystal operating at 4MHz the clock to the COP counter will be 31.25KHz. The value of the COPTO register can be programmed from 1 to 65535 giving a time-out period range from 32µsec minimum to 2.1sec maximum.

Power-On Reset (POR) and Computer Operating Properly (COP), Rev. 4

Operating Modes

7.5.3 COP After Reset

COPCTL is cleared out of reset. Thus the counter is disabled by default. In addition, COPTO is set to it’s maximum value of $FFFF during reset so the counter is loaded with a maximum time-out period when reset is released.

7.5.4 Wait Mode Operation

If both CEN and CWEN are set to one and the Wait mode is entered, the COP counter will continue to count down. If either CEN or CWEN is set to 0 when Wait mode is entered, the counter will be disabled and will reload using the value in the COPTO register.

7.5.5 Stop Mode Operation

If both CEN and CSEN set to one and the Stop mode is entered, the COP counter will continue to count down. If either CEN or CSEN is set to 0 when Stop mode is entered, the counter will be disabled and will reload using the value in the COPTO register.

7.5.6 Debug Mode Operation

The COP counter does not count when the chip is in the Debug mode. Additionally, the CEN bit in the COPCTL always reads as 0 when the chip is in the Debug mode. The actual value of CEN is unaffected by debug however, and it resumes it’s previously set value upon exiting Debug.

7.6 Operating Modes

The COP module design contains two major modes of operation:

•Functional mode

The COP by default is in this mode and will remain in this mode for as long as the SCANTESTMODE input remains low.

•Debug mode

The COP timer is stopped while the processor is in the Debug mode. If the COP is enabled, the timer will resume, counting upon exiting Debug mode. The CEN bit in COPCTL register always reads as 0 when in the Debug mode, even when it has a value of one.

Module Memory Map

7.7 Block Diagram

OSCCLK

IPBus CLK

COP_RST

Figure 7-2. COP Module Block Diagram and Interface Signals

7.8 Module Memory Map

There are three registers on the COP peripheral described in Table 7-2. The registers are summarized in Figure 7-2.

Table 7-2. COP Module Memory Map (COP_BASE = $1FFFD0)