OCCS Resets

6.6.3 Clock Generation Module (CGM) Time-of-Day Register

Figure 6-11. CGM Time-of-Day Register (CGMTOD)

See Programmer’s Sheet on Appendix page B-16

6.6.3.1 Reserved—Bits 15–12

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.6.3.2 TOD Scale Factor (TOD)—Bits 11–0

The output of the oscillator is divided by (TOD + 1) and then divided by 2, generating the TIME_CLK used by the COP module when TOD_SEL is high. The value of TOD should be chosen to result in a TOD clock frequency in the range of 15.12KHz to 31.25KHz. This register is only reset during Power-On Reset (POR).

6.7 OCCS Resets

The CGM registers are reset by a chip level reset. This forces all registers to their reset state and selects the oscillator output as the master clock source for the SIM.

6.8 OCCS Interrupts

The CGM generates a single interrupt request to the INTC. This interrupt is generated by the lock detector circuitry LCK0 and LCK1 outputs and is enabled by the LCK0 Interrupt Enable and LCK1 Interrupt Enable bits in the CGMCR. This interrupt can be used to detect when the PLL goes into lock or when it falls out of lock. The interrupt is cleared by writing 1 to the LCK0 and/or LCK1 bits of the CGMCR.

Chapter 7

Power-On Reset (POR) and

Computer Operating Properly (COP)

Features

7.1 Introduction

The Power-on Reset (POR) function monitors the core power supply, the I/O, and analog power supply. If either of those power supplies are below their thresholds, the POR output for each respective supply is held high. Once the power supply goes above the thresholds, the POR outputs are held low.

Computer Operating Properly (COP) is also discussed in this chapter as it relates to resets.

7.2Features

•The circuit monitors both the core power supply and peripheral power supply

•Holds a wide chip reset once either of these supply voltages are below the thresholds

•Generates the address of the reset vector provided to the core after exit Reset

•The address of reset vector (same as the COP Reset) is located at $1F0000

The COP module design features include:

•Programmable time-out period = (COP_PRESCALER × (CT + 1)) oscillator clock cycles, where CT can be from $0000 to $FFFF

•Programmable Wait and Stop mode operations

•COP timer is disabled while host CPU is in Debug mode

Power-On Reset (POR) and Computer Operating Properly (COP), Rev. 4