6.3 Phase Locked Loop (PLL) Circuit Detail

Phase Locked Loop (PLL) Circuit Detail

6.3.2 Charge Pump

The Charge Pump draws charge into or out of the Loop Filter depending upon the signals from the Phase Frequency Detector. As charge is added to the Loop Filter the Voltage Controlled Oscillator (VCO) control voltage increases. As charge is pulled out of the Loop Filter, the VCO control voltage decreases.

6.3.3 Loop Filter

The Loop Filter produces a voltage proportional to the amount of charge pumped into or out of the Loop Filter by the charge pump. The Loop Filter is a single pole RC filter.

6.3.4 Voltage Controlled Oscillator

The Voltage Controlled Oscillator (VCO) produces a frequency inversely proportional to the value of the control voltage signal coming out of the Loop Filter. The VCO gain is approximately 109MHz/Volt. The VCO has a frequency range of 80MHz to 380MHz with a center frequency of 240MHz.

6.3.5 Down Counter

The Down Counter is a programmable divide by n counter where the divide integer n is user-set to develop the PLL output frequency of interest. By presenting only one return pulse out of n input pulses to the return clock of the phase frequency detector, the PFD will drive the charge pump to raise the VCO frequency until the Down Counter return signal is in frequency and phase lock with the input clock signal. The output of the VCO will, therefore, be n times the frequency of the input clock signal. The value of n has a valid range of 19 to 119. The selected value of n depends upon the desired VCO output frequency and the input clock frequency (Fref). For the 2MHz input crystal the valid range of n will range from 39 to 119, producing a VCO frequency output of 80MHz to 240MHz according to the formula:

Fvco_out = Fref × (n+1)

The VCO’s output frequency is routed through a postscaler so the final PLL output frequency is given by:

Fpll_out = Fvco_out / 2m

where m is the value on the postscaler and can range from 0 to 7.

Example: Let Fref = 32 MHz, n = 4, and m = 3, using the formulas gives:

Fpll_out = (32 MHz × (4+1)) / 8

Fpll_out = 20MHz.

Phase Locked Loop (PLL) Circuit Detail

For the 4MHz input crystal the valid range of n will be from 19 to 59, producing the same VCO output range, 80MHz to 240MHz.

6.3.6 PLL Lock Time User Notes

The PLL’s Voltage Controlled Oscillator (VCO) has a characterized operating range extending from 80MHz to 240MHz. The PLL is programmable via a divide by n+1 register, able to take on values varying between 1 and 128. For higher values of n, PLL lock time becomes an issue. It is recommended to avoid values of n resulting in the VCO frequency being greater than 240MHz. The graphic in Figure 6-7 depicts the range of recommended output frequencies of VCO_OUT, plotting n versus the input frequency (Fref). The lower the value of n, the quicker the PLL will be able to lock.

1000

Fvco_out = 80 Fvco_out = 240

1

Figure 6-7. PLL Output Frequency vs. Input Frequency

The lock time of the PLL is, in many applications, the most critical PLL design parameter. Proper use of the PLL ensures the highest stability and lowest lock time.

CGM Functional Detail

6.3.6.1 PLL Lock Time Determination

Typical control systems refer to the lock time as the reaction time, within specified tolerances, of the system to a step input. In a PLL the step input occurs when the PLL is turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. Therefore, the reaction time is constant in this definition regardless of the size of the step input.

When the PLL is coming from a powered down state (PDN is high) to a powered up condition (PDN is low) the maximum lock time is 10msec.

Other systems refer to lock time as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. Therefore, the lock time varies according to the original error in the output. Minor errors may be shorter or longer in many cases.

6.3.6.2 PLL Parametric Influences on Reaction Time

Lock time is designed to be as short as possible while still providing the highest possible stability. Many factors directly and indirectly affect the lock time.

The most critical parameter affecting the reaction time of the PLL, is the Reference Frequency (Fref). This frequency is the input to the phase detector and controls how often the PLL makes corrections. For stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. Therefore, the slower the Fref, the longer it takes to make these corrections.

Temperature and processing also can affect acquisition time because the electrical characteristics of the PLL change. The part operates as specified as long as these influences stay within the specified limits.

6.4 CGM Functional Detail

The CGM controls the PLL, detects PLL lock, and is used to generate the master clock to the SIM. The CPU clock is one half the frequency of the master clock and the IPBus clock is one fourth the frequency. The SIM handles these clock divisions. The master clock source can be either the oscillator output or the analog PLL output. The oscillator output (Fref) will typically be 4MHz, but a faster active clock can be driven into the XTAL pin at speeds of up to 240MHz. The PLL output can be up to 240MHz.

In order to use the PLL, the proper divide by factor and post scaler values should be programmed into the CGMDB register. Next, the PLL is turned on by setting the Power-Down (PDN) bit in the CGMCR to zero. The user should then wait for the PLL to achieve lock before changing the SEL bit to select the PLL output as the master clock.