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Timing Specifications

 

Table 5-6. Operation with DRV

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

800E Core Operating State

DRV

 

 

 

 

 

 

 

 

Pins

 

 

 

A23:A0

 

 

RD, WR, CSn

D15:D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMI is Between External Memory Accesses

0

Tri-stated

 

 

 

 

Tri-stated

Tri-stated

 

 

Reset Mode

Tri-stated

 

Pulled High Internally

Tri-stated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EMI is Between External Memory Accesses

 

Driven

Driven

 

 

 

 

 

 

 

are Deasserted)

Tri-stated

 

 

(RD,

WR,

CS

1

 

 

 

 

n

 

Reset Mode

Tri-stated

 

Pulled High Internally

Tri-stated

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

5.6.4.2 Base Minimal Delay After Read (BMDAR)—Bits 14–12

This bit field specifies the number of system clocks to delay after reading from memory not in CS controlled space. Since a write to the device implies activating the controller on the bus, this is also considered a read from another device, therefore activating the BMDAR timing control. Please see the description of the MDAR field of the CSTC registers for a discussion of the function of this control.

5.6.4.3 Reserved—Bits 11–10

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.4.4 Base Write Wait States (BWWS)—Bits 9–5

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write access to the selected memory when the memory address does not fall within CS controlled range. The value of BWWS should be set as indicated in Section 5.7.

5.6.4.5 Base Read Wait States (BRWS)—Bits 4–0

This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for read access to the selected memory when the memory address does not fall within CS controlled range. The value of BRWS should be set as indicated in Section 5.7.

5.7 Timing Specifications

5.7.1 Read Timing

5.7.1.1 Consecutive Mode Operation

Figure 5-8 illustrates the read timing for external memory access. For comparison, a single read cycle is illustrated followed by a null cycle and then a back-to-back read.

Figure 5-8 assumes zero wait states are required for the access. Figure 5-9 illustrates a timing diagram with one wait state added.

 

External Memory Interface (EMI), Rev. 4

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Timing Specifications

There are two read setup timing parameters for each read cycle. The core will latch the data on the rising edge of the internal clock while tRSD indicates the core setup time. The external timing of the address and controls is adjusted so they may be changing at this time. Therefore, a data latch is introduced to capture the data (at the pin) a quarter clock earlier, on the rising edge of the internal delayed clock. The setup time required for this latch is illustrated by tRSDP in the

diagrams. For slow clock speeds, tRSDP is more critical, while tRSD may be harder to meet for faster clock rates.

Note: During back-to-back reads, RD remains low to provide the fastest read cycle time.

 

Read (RWS = 0)

 

 

 

 

tC

IDLE

Read (RWS = 0)

Read (RWS = 0)

int_sys_clk

 

 

 

 

int_sys_clk_delay

 

 

 

 

 

tRC

 

 

 

 

tAV

tAV

tCLKA

 

A[23:0]

 

 

 

 

 

tCSV

tCSRH

 

 

CS[7:0]

 

 

 

 

 

tRL

tRH

 

 

RD, OE

 

 

 

 

WR

 

 

 

 

 

tRSDP

 

 

 

 

tRSD

 

 

tRSDP

 

tOEV

tRHD

tRSDP

tRSD

 

tACCESS

tOHZ

tRSD

tACCESS

D[15:0]

Data In

 

Data In

Data In

Figure 5-8. External Read Cycle with Clock and RWS = 0

Note: INT_SYS_CLK is the internal system clock from which everything is referenced.

56852 Digital Signal Controller User Manual, Rev. 4

5-14

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Timing Specifications

 

tC

 

 

 

 

Read (RWS = 1)

IDLE

Read (RWS = 1)

Read (RWS = 1)

int_sys_clk

 

 

 

 

int_sys_clk_delay

 

 

 

 

 

tRC

tAV

 

tCLKA

 

tAV

 

A[23:0], PS, DS

 

 

 

 

 

tCSV

tCSRH

 

 

CS[7:0]

 

 

 

 

 

tRL

tRDH

 

 

 

tRH

 

 

RD, OE

 

 

 

 

WR

 

 

 

 

 

tRSDP

 

 

 

 

tRSD

 

 

 

 

 

 

 

tRSDP

 

tOEV

tOHZ

tRSDP

tRSD

 

tACCESS

tRHD

tRSD

tACCESS

D[15:0]

Data In

 

Data In

Data In

Time added to Figure 5-8 by setting RWS = 1

Figure 5-9. External Read Cycle with RWS = 1, RWSH = 0 and RWSS = 0

5.7.1.2 Read Setup and Hold Timing

Although most memory devices can perform consecutive reads by holding the CSn and RD(OE) signals in the active state and changing the address, there are peripheral devices that require RD(OE) to transition to the inactive state between reads of certain registers. This timing can be accommodated with the Read Setup (RWSS) and/or Read Hold (RWSH) control fields illustrated in Figure 5-10 and Figure 5-11.

External Memory Interface (EMI), Rev. 4

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5-15

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Timing Specifications

int_sys_clk

int_sys_clk_delay

A[23:0], PS, DS

CS[7:0]

RD, OE

WR

D[15:0]

 

IDLE

Read (RWSS = RWS = 1)

Read (RWSS = RWS = 1)

 

Read (RWSS = RWS = 1)

tRC

 

 

tAV

tAV

 

t

tCSRH

 

CSV

 

 

tRL

tRH

 

tOEV

 

 

tRSD

 

tOEV

 

 

tRSD

 

 

tRSDP

 

 

 

 

 

 

 

 

 

tRSD

 

 

 

 

 

 

 

 

tRSDP

 

 

 

 

 

 

 

 

 

 

 

 

tACCESS

tOHZ

 

 

 

 

 

tRSDP

 

 

 

 

 

 

 

tACCESS

 

 

 

 

 

 

 

 

 

 

Data In

 

 

 

 

 

 

 

Data In

 

 

 

 

 

Data In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Time added to by setting RWSS = 1

Figure 5-10. External Read Cycle with RWSS = RWS = 1, and RWSH = 0

 

56852 Digital Signal Controller User Manual, Rev. 4

5-16

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Timing Specifications

 

 

 

IDLE

Read (RWS = RWSH = 1)

 

Read (RWS = RWSH = 1)

Read (RWS = RWSH = 1)

 

int_sys_clk

 

 

 

 

int_sys_clk_delay

 

 

 

 

 

tRC

 

 

 

 

tAV

 

tAV

 

A[23:0], PS, DS

 

 

 

 

 

t

 

tCSRH

 

 

CSV

 

 

 

CS[7:0]

 

 

 

 

 

tRL

tRH

 

 

RD, OE

 

 

 

 

WR

 

 

 

 

 

tRSDP

 

 

 

 

tRSD

 

 

tRSDP

 

 

 

 

tRSD

 

tOEV

 

tRSDP

tOEV

 

tACCESS

tOHZ

tRSD

tACCESS

D[15:0]

Data In

 

Data In

Data In

Time added to Figure 5-10 by setting RWSH = 1

Figure 5-11. External Read Cycle RWS = RWSH = 1 and RWSS = 0

5.7.2 Write Timing

Figure 5-12 shows the write timing for external memory access. For comparison, a single write cycle is shown followed by a null cycle and then a back-to-back write.This figure assumes zero wait states are required for the access.

External Memory Interface (EMI), Rev. 4

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5-17

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prior to September

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Timing Specifications

 

tC

 

 

 

 

IDLE

 

 

 

 

 

 

 

Write (WWS = 0)

 

 

IDLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write (WWS = 0)

 

 

 

 

 

 

 

 

 

 

Write (WWS = 0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

int_sys_clk(core) int_delay_SEMI_clk

 

tWC

tAV

tAV

A[23:0]

RD = OE

t

 

 

 

tWHZ

 

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WDE

 

 

 

 

 

WDO

 

 

 

tWDE

t

WDO

 

 

 

 

 

 

 

tWHZ

 

 

D[16:0]

 

 

 

tCSL

 

tCSV

tCSV

 

CS2

 

 

 

tDH

tAVW

 

tDW

tDH

 

 

 

tWRL

 

 

 

 

 

 

 

tWRH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCWH

 

 

 

 

 

 

tDW

tCWL

 

 

 

t

 

 

 

 

 

 

 

 

 

 

 

 

 

 

t

 

 

 

CWL

 

 

 

 

 

 

 

 

 

 

 

tAVW

 

 

 

 

 

 

 

 

 

 

 

WAC

 

 

 

tAVW

 

 

 

 

 

 

 

tCWH

 

 

 

 

 

 

 

 

 

 

 

 

WR

Figure 5-12. External Write Cycle

Note: When WWS = 0 the timing of the WR strobe is generated from different clock edges than when it is set to some other value. This change in timing allows the possibility of single cycle write operation, but reduces the pulse width of WR to one quarter clock. This may make it difficult to meet write timing requirements for most devices when operating at normal clock rates.

56852 Digital Signal Controller User Manual, Rev. 4

5-18

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Timing Specifications

Write (WWS = 1)

 

tC

IDLE

int_sys_clk(core)

 

int_delay_SEMI_clk

 

tWC

tAV

tAV

A[23:0]

 

RD = OE

 

tWDE

tWHZ

tWDO

 

D[16:0]

 

tCSL

 

tCSV

tCSV

CS2

 

tDW

tCWH

tWRL

 

tCWL

tDH

tAVW

WR

 

Write (WWS = 1) Write (WWS = 1) IDLE

 

 

tWDO

tWHZ

 

 

 

 

tDH

 

tWAC

tDW

tCWH

tWRL

tWRH

 

tCWH

tCWL

tAVW

tAVW

 

 

Time added to Figure 5-12 by setting WWS = 1

Figure 5-13. External Write Cycle with WWS = 1, WWSH = 0, and WWSS = 0

5.7.2.1 Write Setup and Hold Timing

Since the timing of the strobes is different when WWS = 0 than it is when WWS > 0, two sets of timing diagrams are illustrated in Figure 5-14, Figure 5-15, Figure 5-16, and Figure 5-17.

5.7.2.2 WWS = 0

Although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. The WWSS and WWSH field of the CSTC register provides the ability to allow for a write setup and/or hold time requirement as shown in

Figure 5-14 and Figure 5-15.

 

External Memory Interface (EMI), Rev. 4

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5-19

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Because

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Timing Specifications

 

 

 

 

 

 

 

 

 

 

 

 

IDLE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tC

 

 

 

IDLE

 

 

 

Write (WWSS=1,WWS=0)

 

 

 

 

 

 

 

 

Write (WWSS=1,WWS=0)

Write (WWSS=1,WWS=0)

 

 

 

35.7 MHz INT_SYS_CLK(core)

 

 

 

 

 

int_delay_SEMI_clk

 

 

 

 

 

 

 

tAV(4.3)

 

 

 

 

 

 

 

tWC

tAV(4.3)

 

 

 

 

 

 

A[23:0]

 

 

 

 

 

RD_B

=

OE_B

 

 

 

 

 

 

 

tWDE

tWHZ(3)

 

 

 

tWHZ(3)

 

 

tWDO(6.5+6.3)

 

tWDO(6.5+6.3)

 

 

D[16:0]

 

 

 

 

 

 

 

tCSV(4.3)

 

 

 

 

 

 

 

tCSL

tCSV(4.3)

 

 

 

 

 

 

CS2_B

 

 

 

 

 

 

 

 

tDH(0)

 

tAVW(0)

 

 

 

 

 

tWRL(7)

 

tDH(0)

 

 

 

 

tDW(3)

tCWH(4.3)

tDW(3)

tWRH(7)

tCWH(4.3)

 

 

tAVW(0)

tCWL(4.3)

tAVW(0)

tCWL(4.3)

 

tWAC

 

 

WR_B

 

 

 

 

 

Time added to Figure 5-12 by setting WWSS = 1

Figure 5-14. External Write Cycle with WWSS = 1, WWS = 0 and WWSH = 0

56852 Digital Signal Controller User Manual, Rev. 4

5-20

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2010: MC13892

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Timing Specifications

IDLE

tC

IDLE

Write (WWS=0,WWSH=1)

 

Write (WWS=0,WWSH=1)

Write (WWS=0,

int_sys_clk(core)

 

WWSH=1)

 

 

int_delay_SEMI_clk

 

 

tAV

 

 

tWC

tAV

 

A[23:0]

 

 

RD = OE

 

 

tWDE

tWHZ

tWHZ

tWDO

tWDE

tWDO

D[16:0]

 

 

tCSV

 

 

tCSL

tCSV

 

CS2

 

 

tCWH

 

 

 

 

tDH

 

 

 

 

 

 

 

tDH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDW

 

 

 

 

 

 

 

tWRH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDW

 

 

tCWH

tCWL

 

 

 

 

 

 

 

 

 

 

 

 

 

tWRL

 

 

 

 

tCWL

 

 

 

 

 

 

 

 

 

tWAC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tAVW

 

 

 

 

tAVW

 

 

 

 

 

 

tAVW

 

 

 

 

 

 

WR

Time added to Figure 5-12 by setting WWSS = 1

Figure 5-15. External Write Cycle with WWS = 0, WWSH = 1, WWSS = 0

5.7.2.3 WWS > 0

Although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. The WWSS and WWSH field of the CSTC register provides the ability to allow for a write setup and/or hold time requirement as shown in

Figure 5-16 and Figure 5-17 respectively.

External Memory Interface (EMI), Rev. 4

Freescale Semiconductor

5-21

-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

prior to September

order from the United States International Trade Freescale for import or sale in the United States

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Timing Specifications

INT_SYS_CLK(core)

int_delay_SEMI_clk

A[23:0]

RD = OE

D[16:0]

CS2

WR

 

 

Write (WWSS = WWS = 1)

 

 

IDLE

 

 

IDLE

Write (WWSS = WWS = 1)

 

 

Write(WWSS = WWS = 1)

 

 

tAV

 

tAV

 

 

 

 

tWDE

 

tWHZ

 

 

tWHZ

 

tWDO

 

 

 

 

tWDO

 

tCSL

 

 

 

 

 

 

tCSV

 

tCSV

 

 

 

 

 

t

tDH

 

tWRH

tDH

 

 

WRL

 

t

 

tCWL

 

t

AVW

t

 

 

 

 

WAC

tDW

 

 

CWL

 

 

 

 

tAVW

tDH

tWRL

 

t

t

CWH

tDW

 

tDW

 

AVW

 

 

 

 

 

Time added to Figure 5-13 by setting WWSS = 1

Figure 5-16. External Write Cycle with WWSS = WWS = 1 and WWSH = 0

 

56852 Digital Signal Controller User Manual, Rev. 4

5-22

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-packaged product lines and part numbers indicated here currently are not

2010: MC13892

Commission, BGA

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