
- •Preface
- •About This Manual
- •Audience
- •Manual Organization
- •Suggested Reading
- •Manual Conventions
- •1.1 Introduction
- •1.2 56800E Core Description
- •1.3 56852 Architectural Overview
- •1.4 System Bus Controller
- •1.5 56852 Memory
- •1.6 56852 Peripheral Blocks
- •2.1 Introduction
- •2.2 Features
- •2.3 Signal and Package Information
- •3.1 Introduction
- •3.2 Program Boot ROM
- •3.3 Memory Map
- •4.1 Introduction
- •4.2 Features
- •4.3 SIM Block Diagram
- •4.4 Signal Description
- •4.5 Module Memory Map
- •4.6 Register Descriptions (SYS_BASE = $1FFF08)
- •4.7 Implementation
- •4.8 Generated Clocks
- •4.9 Generated Resets
- •4.10 Power Mode Controls
- •5.1 Introduction
- •5.2 Features
- •5.3 Functional Description
- •5.4 Block Diagram
- •5.5 Module Memory Map
- •5.6 Register Descriptions (EMI_BASE = $1FFE40)
- •5.7 Timing Specifications
- •5.8 Clocks
- •5.9 Interrupts
- •5.10 Resets
- •6.1 Introduction
- •6.2 OSC (Oscillator) Circuit Detail
- •6.3 Phase Locked Loop (PLL) Circuit Detail
- •6.4 CGM Functional Detail
- •6.5 Module Memory Map
- •6.6 Register Descriptions (CGM_BASE = $1FFF10)
- •6.7 OCCS Resets
- •6.8 OCCS Interrupts
- •7.1 Introduction
- •7.2 Features
- •7.3 Block Diagram
- •7.4 Method of Operation
- •7.5 Computer Operating Properly (COP) Module
- •7.6 Operating Modes
- •7.7 Block Diagram
- •7.8 Module Memory Map
- •7.9 Register Descriptions (COP_BASE = $1FFFD0)
- •7.10 Clocks
- •7.11 Resets
- •7.12 Interrupts
- •8.1 Introduction
- •8.2 Features
- •8.3 ITCN Module Signal Description
- •8.4 Block Diagram
- •8.5 Functional Description
- •8.6 Operating Modes
- •8.7 Wait and Stop Modes Operations
- •8.8 Module Memory Map
- •8.9 Register Descriptions (ITCN_BASE = $1FFF20)
- •8.10 Resets
- •8.11 Interrupts
- •9.1 Introduction
- •9.2 Features
- •9.3 Block Diagram
- •9.4 Signal Descriptions
- •9.5 Functional Description
- •9.6 Low Power Modes
- •9.7 Module Memory Map
- •9.8 Register Descriptions (SCI_BASE = $1FFFE0)
- •9.9 Clocks
- •9.10 Resets
- •9.11 Interrupts
- •10.1 Introduction
- •10.2 Features
- •10.3 SPI Block Diagram
- •10.4 Signal Descriptions
- •10.5 External I/O Signals
- •10.6 Operating Modes
- •10.7 Transmission Formats
- •10.8 Transmission Data
- •10.9 Error Conditions
- •10.10 Module Memory Map
- •10.11 Registers Descriptions (SPI_BASE = $1FFFE8)
- •10.12 Resets
- •10.13 Interrupts
- •11.1 Introduction
- •11.2 Features
- •11.3 Signal Descriptions
- •11.4 Block Diagram
- •11.5 ISSI Configurations
- •11.6 Module Memory Map
- •11.7 Register Descriptions (ISSI_BASE = $1FFE20)
- •11.8 ISSI Operating Modes
- •11.9 Clocks
- •11.10 Clock Operation Description
- •11.11 Resets
- •11.12 Interrupts
- •11.13 User Notes
- •12.1 Introduction
- •12.2 Features
- •12.3 Operating Modes
- •12.4 Block Diagram
- •12.5 Signal Description
- •12.6 Functional Description
- •12.7 Counting Modes Definitions
- •12.8 Module Memory Map
- •12.9 Register Descriptions (TMR_BASE = $1FFE80)
- •12.10 Resets
- •12.11 Interrupts
- •13.1 Introduction
- •13.2 Features
- •13.3 GPIO Block Diagram
- •13.4 Functional Description
- •13.5 Modes of Operation
- •13.6 GPIO Configurations
- •13.7 Module Memory Maps
- •13.8 Register Descriptions
- •13.9 Data Register Access
- •13.10 Resets
- •13.11 Interrupts
- •14.1 Introduction
- •14.2 Features
- •14.3 Master Test Access Port (TAP)
- •14.4 TAP Block Diagram
- •14.5 JTAG Port Architecture
- •14.6 JTAG Bypass Register (JTAGBR)
- •14.7 JTAG Boundary Scan Register (BSR)
- •14.8 TAP Controller
- •14.9 56852 Restrictions
- •B.1 Introduction
- •B.2 Programmer’s Sheets

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Timing Specifications |
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Table 5-6. Operation with DRV |
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800E Core Operating State |
DRV |
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Pins |
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A23:A0 |
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RD, WR, CSn |
D15:D0 |
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EMI is Between External Memory Accesses |
0 |
Tri-stated |
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Tri-stated |
Tri-stated |
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Reset Mode |
Tri-stated |
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Pulled High Internally |
Tri-stated |
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EMI is Between External Memory Accesses |
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Driven |
Driven |
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are Deasserted) |
Tri-stated |
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(RD, |
WR, |
CS |
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1 |
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n |
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Reset Mode |
Tri-stated |
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Pulled High Internally |
Tri-stated |
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5.6.4.2 Base Minimal Delay After Read (BMDAR)—Bits 14–12
This bit field specifies the number of system clocks to delay after reading from memory not in CS controlled space. Since a write to the device implies activating the controller on the bus, this is also considered a read from another device, therefore activating the BMDAR timing control. Please see the description of the MDAR field of the CSTC registers for a discussion of the function of this control.
5.6.4.3 Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.4.4 Base Write Wait States (BWWS)—Bits 9–5
This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write access to the selected memory when the memory address does not fall within CS controlled range. The value of BWWS should be set as indicated in Section 5.7.
5.6.4.5 Base Read Wait States (BRWS)—Bits 4–0
This bit field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for read access to the selected memory when the memory address does not fall within CS controlled range. The value of BRWS should be set as indicated in Section 5.7.
5.7 Timing Specifications
5.7.1 Read Timing
5.7.1.1 Consecutive Mode Operation
Figure 5-8 illustrates the read timing for external memory access. For comparison, a single read cycle is illustrated followed by a null cycle and then a back-to-back read.
Figure 5-8 assumes zero wait states are required for the access. Figure 5-9 illustrates a timing diagram with one wait state added.
|
External Memory Interface (EMI), Rev. 4 |
Freescale Semiconductor |
5-13 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
There are two read setup timing parameters for each read cycle. The core will latch the data on the rising edge of the internal clock while tRSD indicates the core setup time. The external timing of the address and controls is adjusted so they may be changing at this time. Therefore, a data latch is introduced to capture the data (at the pin) a quarter clock earlier, on the rising edge of the internal delayed clock. The setup time required for this latch is illustrated by tRSDP in the
diagrams. For slow clock speeds, tRSDP is more critical, while tRSD may be harder to meet for faster clock rates.
Note: During back-to-back reads, RD remains low to provide the fastest read cycle time.
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Read (RWS = 0) |
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tC |
IDLE |
Read (RWS = 0) |
Read (RWS = 0) |
int_sys_clk |
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int_sys_clk_delay |
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tRC |
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tAV |
tAV |
tCLKA |
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A[23:0] |
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tCSV |
tCSRH |
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CS[7:0] |
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tRL |
tRH |
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RD, OE |
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WR |
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tRSDP |
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tRSD |
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tRSDP |
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tOEV |
tRHD |
tRSDP |
tRSD |
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tACCESS |
tOHZ |
tRSD |
tACCESS |
D[15:0] |
Data In |
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Data In |
Data In |
Figure 5-8. External Read Cycle with Clock and RWS = 0
Note: INT_SYS_CLK is the internal system clock from which everything is referenced.
56852 Digital Signal Controller User Manual, Rev. 4
5-14 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
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tC |
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Read (RWS = 1) |
IDLE |
Read (RWS = 1) |
Read (RWS = 1) |
int_sys_clk |
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int_sys_clk_delay |
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tRC |
tAV |
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tCLKA |
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tAV |
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A[23:0], PS, DS |
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tCSV |
tCSRH |
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CS[7:0] |
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tRL |
tRDH |
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tRH |
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RD, OE |
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WR |
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tRSDP |
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tRSD |
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tRSDP |
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tOEV |
tOHZ |
tRSDP |
tRSD |
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tACCESS |
tRHD |
tRSD |
tACCESS |
D[15:0] |
Data In |
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Data In |
Data In |
Time added to Figure 5-8 by setting RWS = 1
Figure 5-9. External Read Cycle with RWS = 1, RWSH = 0 and RWSS = 0
5.7.1.2 Read Setup and Hold Timing
Although most memory devices can perform consecutive reads by holding the CSn and RD(OE) signals in the active state and changing the address, there are peripheral devices that require RD(OE) to transition to the inactive state between reads of certain registers. This timing can be accommodated with the Read Setup (RWSS) and/or Read Hold (RWSH) control fields illustrated in Figure 5-10 and Figure 5-11.
External Memory Interface (EMI), Rev. 4
Freescale Semiconductor |
5-15 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
int_sys_clk
int_sys_clk_delay
A[23:0], PS, DS
CS[7:0]
RD, OE
WR
D[15:0]
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IDLE |
Read (RWSS = RWS = 1) |
Read (RWSS = RWS = 1) |
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Read (RWSS = RWS = 1) |
tRC |
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tAV |
tAV |
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t |
tCSRH |
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CSV |
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tRL |
tRH |
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tOEV |
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tRSD |
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tOEV |
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tRSD
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tRSDP |
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tRSD |
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tRSDP |
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tACCESS |
tOHZ |
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tRSDP |
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tACCESS |
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Data In |
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Data In |
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Data In |
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Time added to by setting RWSS = 1
Figure 5-10. External Read Cycle with RWSS = RWS = 1, and RWSH = 0
|
56852 Digital Signal Controller User Manual, Rev. 4 |
5-16 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
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IDLE |
Read (RWS = RWSH = 1) |
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Read (RWS = RWSH = 1) |
Read (RWS = RWSH = 1) |
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int_sys_clk |
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int_sys_clk_delay |
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tRC |
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tAV |
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tAV |
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A[23:0], PS, DS |
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t |
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tCSRH |
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CSV |
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CS[7:0] |
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tRL |
tRH |
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RD, OE |
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WR |
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tRSDP |
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tRSD |
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tRSDP |
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tRSD |
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tOEV |
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tRSDP |
tOEV |
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tACCESS |
tOHZ |
tRSD |
tACCESS |
D[15:0] |
Data In |
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Data In |
Data In |
Time added to Figure 5-10 by setting RWSH = 1
Figure 5-11. External Read Cycle RWS = RWSH = 1 and RWSS = 0
5.7.2 Write Timing
Figure 5-12 shows the write timing for external memory access. For comparison, a single write cycle is shown followed by a null cycle and then a back-to-back write.This figure assumes zero wait states are required for the access.
External Memory Interface (EMI), Rev. 4
Freescale Semiconductor |
5-17 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
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tC |
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IDLE |
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Write (WWS = 0) |
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IDLE |
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Write (WWS = 0) |
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Write (WWS = 0) |
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int_sys_clk(core) int_delay_SEMI_clk
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tWC |
tAV |
tAV |
A[23:0]
RD = OE
t |
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tWHZ |
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t |
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WDE |
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WDO |
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tWDE |
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t |
WDO |
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tWHZ |
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D[16:0] |
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tCSL |
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tCSV |
tCSV |
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CS2 |
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tDH |
tAVW |
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tDW |
tDH |
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tWRL |
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tWRH |
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tCWH |
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tDW |
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tCWL |
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t |
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t |
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CWL |
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tAVW |
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WAC |
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tAVW |
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tCWH |
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WR
Figure 5-12. External Write Cycle
Note: When WWS = 0 the timing of the WR strobe is generated from different clock edges than when it is set to some other value. This change in timing allows the possibility of single cycle write operation, but reduces the pulse width of WR to one quarter clock. This may make it difficult to meet write timing requirements for most devices when operating at normal clock rates.
56852 Digital Signal Controller User Manual, Rev. 4
5-18 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
Write (WWS = 1) |
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tC |
IDLE |
int_sys_clk(core) |
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int_delay_SEMI_clk |
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tWC |
tAV |
tAV |
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A[23:0] |
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RD = OE |
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tWDE |
tWHZ |
tWDO |
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D[16:0] |
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tCSL |
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tCSV |
tCSV |
CS2 |
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tDW |
tCWH |
tWRL |
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tCWL |
tDH |
tAVW |
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WR |
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Write (WWS = 1) Write (WWS = 1)
IDLE
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tWDO |
tWHZ |
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tDH |
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tWAC |
tDW |
tCWH |
tWRL |
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tWRH |
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tCWH |
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tCWL |
tAVW |
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tAVW |
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Time added to Figure 5-12 by setting WWS = 1
Figure 5-13. External Write Cycle with WWS = 1, WWSH = 0, and WWSS = 0
5.7.2.1 Write Setup and Hold Timing
Since the timing of the strobes is different when WWS = 0 than it is when WWS > 0, two sets of timing diagrams are illustrated in Figure 5-14, Figure 5-15, Figure 5-16, and Figure 5-17.
5.7.2.2 WWS = 0
Although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. The WWSS and WWSH field of the CSTC register provides the ability to allow for a write setup and/or hold time requirement as shown in
Figure 5-14 and Figure 5-15.
|
External Memory Interface (EMI), Rev. 4 |
Freescale Semiconductor |
5-19 |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
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IDLE |
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tC |
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IDLE |
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Write (WWSS=1,WWS=0) |
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Write (WWSS=1,WWS=0) |
Write (WWSS=1,WWS=0) |
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35.7 MHz INT_SYS_CLK(core) |
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int_delay_SEMI_clk |
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tAV(4.3) |
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tWC |
tAV(4.3) |
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A[23:0] |
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RD_B |
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OE_B |
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tWDE |
tWHZ(3) |
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tWHZ(3) |
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tWDO(6.5+6.3) |
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tWDO(6.5+6.3) |
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D[16:0] |
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tCSV(4.3) |
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tCSL |
tCSV(4.3) |
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CS2_B |
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tDH(0) |
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tAVW(0) |
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tWRL(7) |
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tDH(0) |
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tDW(3) |
tCWH(4.3) |
tDW(3) |
tWRH(7) |
tCWH(4.3) |
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tAVW(0) |
tCWL(4.3) |
tAVW(0) |
tCWL(4.3) |
|
tWAC |
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WR_B |
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|
Time added to Figure 5-12 by setting WWSS = 1
Figure 5-14. External Write Cycle with WWSS = 1, WWS = 0 and WWSH = 0
56852 Digital Signal Controller User Manual, Rev. 4
5-20 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |

Timing Specifications
IDLE
tC |
IDLE |
Write (WWS=0,WWSH=1) |
|
Write (WWS=0,WWSH=1) |
Write (WWS=0, |
int_sys_clk(core) |
|
WWSH=1) |
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|
|
int_delay_SEMI_clk |
|
|
tAV |
|
|
tWC |
tAV |
|
A[23:0] |
|
|
RD = OE |
|
|
tWDE |
tWHZ |
tWHZ |
tWDO |
tWDE |
tWDO |
D[16:0] |
|
|
tCSV |
|
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tCSL |
tCSV |
|
CS2 |
|
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tCWH |
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tDH |
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tDH |
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tDW |
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tWRH |
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||
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tDW |
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tCWH |
||||||||||
tCWL |
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tWRL |
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tCWL |
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tWAC |
|||
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|||||||||||||||
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tAVW |
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tAVW |
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tAVW |
|||||||
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WR
Time added to Figure 5-12 by setting WWSS = 1
Figure 5-15. External Write Cycle with WWS = 0, WWSH = 1, WWSS = 0
5.7.2.3 WWS > 0
Although most memory devices require a zero setup and hold time, there are some peripheral devices where a setup/hold time is required. The WWSS and WWSH field of the CSTC register provides the ability to allow for a write setup and/or hold time requirement as shown in
Figure 5-16 and Figure 5-17 respectively.
External Memory Interface (EMI), Rev. 4
Freescale Semiconductor |
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-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
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Because |
available |

Timing Specifications
INT_SYS_CLK(core)
int_delay_SEMI_clk
A[23:0]
RD = OE
D[16:0]
CS2
WR
|
|
Write (WWSS = WWS = 1) |
||
|
|
|||
IDLE |
|
|
IDLE |
|
Write (WWSS = WWS = 1) |
|
|
Write(WWSS = WWS = 1) |
|
|
|
tAV |
|
tAV |
|
|
|
|
tWDE |
|
tWHZ |
|
|
tWHZ |
|
tWDO |
|
|
|
|
tWDO |
|
tCSL |
|
|
|
|
|
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tCSV |
|
tCSV |
|
|
|
|
|
t |
tDH |
|
tWRH |
tDH |
|
|
WRL |
|
t |
|
||
tCWL |
|
t |
AVW |
t |
|
|
|
|
|
WAC |
|||
tDW |
|
|
CWL |
|
|
|
|
|
tAVW |
tDH |
tWRL |
|
|
t |
t |
CWH |
tDW |
|
tDW |
|
AVW |
|
|
|
|
|
Time added to Figure 5-13 by setting WWSS = 1
Figure 5-16. External Write Cycle with WWSS = WWS = 1 and WWSH = 0
|
56852 Digital Signal Controller User Manual, Rev. 4 |
5-22 |
Freescale Semiconductor |
-packaged product lines and part numbers indicated here currently are not |
2010: MC13892 |
Commission, BGA |
prior to September |
order from the United States International Trade Freescale for import or sale in the United States |
|
of an from |
|
Because |
available |