Register Descriptions (EMI_BASE = $1FFE40)

Figure 5-2. EMI Register Map Summary

5.6 Register Descriptions (EMI_BASE = $1FFE40)

5.6.1 Chip Select Base Address Registers 0–3 (CSBAR0–CSBAR3)

The CSBAR registers are defined in Figure 5-3. It determines the active address range of a given CSn. The Block Size (BLKSZ) field determines the size of the memory map covered by the CSn. This field also determines which of the address bits to use when specifying the base address of the CSn. This encoding is detailed in Table 5-2. When the active bits match the address and the constraints specified in the CSOR are also met, the CSn is asserted.

The chip-select address compare logic uses only the most significant bits to match an address within a block. The value of the base address must be an integer multiple of the block size (i.e., the base address can be at block size boundaries only). For example, for a block size of 64k, the base address can be 64k, 128k, 192k, 256k, 320k, etc.

Register Descriptions (EMI_BASE = $1FFE40)

Note: The default reset value for CSn will enable a 32K block of external memory starting at address zero. This may be defined to be something else for a specific chip in which case the chip user manual will detail the specific reset value.

Figure 5-3. Chip Select Base Address Registers 0–3 (CSBAR0–CSBAR3)

See Programmer’s Sheet on Appendix page B-9

Table 5-2. CSBAR Encoding of the BLKSZ Field

5.6.2 Chip Select Option Registers 0–3 (CSOR0–CSOR3)

A Chip Select Option Register is required for every chip select. This register specifies the mode of operation of the chip select and the timing requirements of the external memory.

Note: The CSn logic can be used to define external memory wait states even if the CSn pin is used as GPIO.

Note: The CSn output can be disabled by setting either the PS/DS, R/W or BYTE_EN fields to zero.

Register Descriptions (EMI_BASE = $1FFE40)

Figure 5-4. Chip Select Option Registers 0–3 (CSOR0–CSOR3)

See Programmer’s Sheet on Appendix page B-10

5.6.2.1 Read Wait States (RWS)—Bits 15–11

The RWS field specifies the number of additional system clocks, 0-30 (31 is invalid) to delay for read access to the selected memory. The value of RWS should be set as indicated in Section

5.7.1.

5.6.2.2 Upper/Lower Byte Option (BYTE_EN)—Bits 10–9

This field specifies whether the memory is 16 bits wide or one byte wide. If the memory is byte wide, the option of upper or lower byte of a 16-bit word is selectable. Table 5-3 provides the encoding of this field.

Table 5-3. CSOR Encoding BYTE_EN Values

5.6.2.3 Read/Write Enable (R/W)—Bits 8–7

This field determines the read/write capabilities of the associated memory as shown in Table 5-4.

Table 5-4. CSOR Encoding of Read/Write Values

Register Descriptions (EMI_BASE = $1FFE40)

5.6.2.4 Program/Data Space Select (PS/DS)—Bits 6–5

The mapping of a chip select to program and/or data space is shown in Table 5-5.

Table 5-5. CSOR Encoding of PS/DS Values

5.6.2.5 Write Wait States (WWS)—Bits 4–0

The WWS field specifies the number of additional system clocks 0-30 (31 is invalid) to delay for write access to the selected memory. The value of WWS should be set as indicated in Section

5.7.2.

5.6.3 Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)

A Chip Select Timing Control (CSTC) register is required for every chip select. This register specifies the detailed timing required for accessing devices in the selected memory map. At reset, these registers are configured for minimal timing in the external access waveforms. Therefore, these registers need only be adjusted if required by slower memory/peripheral devices.

Figure 5-5. Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)

See Programmer’s Sheet on Appendix page B-11

5.6.3.1 Write Wait States Setup Delay (WWSS)—Bits 15–14

This field affects the write cycle timing diagram, illustrated in Figure 5-16. Additional time (clock cycles) is provided between the assertion of CSn and address lines and the assertion of WR. The value of WWSS should be set as indicated in Section 5.7.2.

Register Descriptions (EMI_BASE = $1FFE40)

5.6.3.2 Write Wait States Hold Delay (WWSH)—Bits 13–12

This field affects the write cycle timing diagram, illustrated in Figure 5-17. The WWSH field specifies the number of additional system clocks to hold the address, data, and CSn signals after the WR signal is deasserted. The value of WWSH should be set as indicated in Section 5.7.2.

5.6.3.3 Read Wait States Setup Delay (RWSS)—Bits 11–10

This field affects the read cycle timing diagram, illustrated in Figure 5-10. Additional time (clock cycles) is provided between the assertion of CSn and address lines and the assertion of RD. The value of RWSS should be set as indicated in Section 5.7.1.

5.6.3.4 Read Wait States Hold Delay (RWSH)—Bits 9–8

This field affects the read cycle timing diagram, illustrated in Figure 5-11. The RWSH field specifies the number of additional system clocks to hold the address, data, and CSn signals after the RD signal is deasserted. The value of RWSH should be set as indicated in Section 5.7.1.

Note: If both, the RWSS and RWSH fields are set to zero the EMI read timing is set for consecutive mode. In this mode the RD signal will remain active during back-to-back reads from the same CSn controlled memory space.

5.6.3.5 Reserved—Bits 7–3

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.3.6 Minimal Delay After Read (MDAR)—Bits 2–0

This field specifies the number of system clocks to delay between reading from memory in a CSn controlled space and reading from another device. Since a write to the device implies activating the controller on the bus, this is also considered a read from another device.

Figure 5-6 illustrates the timing issue requiring the introduction of the MDAR field. In this diagram, CS1 is assumed to operate a slow flash memory in P-space while CS2 is operating a faster RAM in X-space. In some bus contention cases, it is possible to encounter data integrity problems where the contention is occurring at the time the data bus is sampled.

Register Descriptions (EMI_BASE = $1FFE40)

RAM READ

FLASH READ

INT_SEMI_CLK

FLASH CS1

Bus Contention with two devices driving data at the same time.

Figure 5-6. Data Bus Contention Timing Requiring MDAR Field Assertion

5.6.4 Bus Control Register (BCR)

The BCR register defines the default read timing for external memory accesses to addresses not covered by the CS/CSOR/CSTC registers. The timing specified by the BCR register applies to both program and data space accesses because the PS and DS control signals are not directly available on the chip pinouts.

Note: Any of the CSn signals can be configured to mirror the PS and/or DS function, but then the associated CSn configuration registers control the timing.

Figure 5-7. Bus Control Register (BCR)

See Programmer’s Sheet on Appendix page B-12

5.6.4.1 Drive (DRV)—Bit 15

The Drive (DRV) control bit is used to specify what occurs on the external memory port pins when no external access is performed (whether the pins remain driven or are placed in tri-state). Table 5-6 summarizes the action of the EMI when the DRV bit is cleared or is set. DRV bit is cleared on hardware reset, but should be set in most customer applications.

56852 Digital Signal Controller User Manual, Rev. 4