Power Mode Controls

The reset generation module has two reset detectors:

1.A chip internal reset is detected when any of the sources assert.

2.A POR reset is detected only when the Power-On Reset input asserts and 32-input clocks have been observed.

The detectors assert asynchronously to asynchronous sources and synchronously to synchronous sources. They always deassert synchronously. They remain asserted until the last active reset source deasserts. The chip-internal reset detector output is the primary reset used within the SIM. The software control registers are reset by the POR reset detector.

The SIM generates four reset outputs. All are active low. These all are activated by one of the two detectors but remain asserted for 32-system clock cycles after the detector deasserts. This permits the SIM to generate 32-system clock cycles of continuous clocking to the part while the reset remains asserted. This is required to clear synchronous resets within the core and elsewhere in the part. The RST_CORE, RST_PERIPH. RST_CGM outputs are activated by the chip-internal reset detector. The RST_CORE output is used to reset the core. The RST_CGM is used to reset the CGM module. The RST_PERIPH reset is used to reset everything else.

JTAG standards require the part to be held in reset during external boundary scan operations. When the BSCAN_EBL input is asserted, all resets used within the SIM and all reset outputs of the SIM will go to their active asserted state. This prevents accidental damage due to random inputs applied during boundary scan testing.

The Software Reset is only operable in the Run mode when the CPU is able to write to the SIM control register to activate the Software Reset.

4.10 Power Mode Controls

The Power Mode Control module controls movement between the three power modes supported by the core:

•Run mode provides full functionality

•Wait mode disables

—execution of the core

—any unnecessary system clocks

•Stop mode disables

—56800E core

—all system clocks

—peripheral bus clock

Power Mode Controls

—PLL optionally

—OSC optionally

The time-based clock generated by the oscillator and Clock Generation Module (CGM) are not affected by Low Power modes. Time based functions such as the Computer Operating Properly (COP) module must be individually disabled for maximum low-power effects. Likewise, Power Mode Controls do not affect pull-up/pull-down resistor enabling. Power loss through input and bidirectional I/O cell pull-up/pull-down resistors can be eliminated by disabling the resistor in the software where supported, or in the case of bidirectional I/O, by putting the cell in an output state and avoiding external contention.

When the core executes a Stop or Wait instruction it will wait until any stall or hold-off activity has completed (c7WAITST has deasserted) then assert the p5STOP or p5WAIT SIM input and the SIM will enter the corresponding Low Power mode. The SIM Control register also contains Stop and Wait disable bits. When asserted, these cause the core to ignore Stop and Wait instructions.

Recovery from the Stop or Wait modes automatically reverts to the Run mode if there is a:

•Pending enabled interrupt (INT_PEND input asserts) e.g. Level Sensitive IRQA/IRQB asserts

•Debug mode request from the core due to a JTAG initiated the Debug mode entry request (jtdebreq input asserts)

•Debug mode entry request from the DE input pad (DE asserts)

•COP Time-out

The SIM has special control relationships with both the Oscillator (OSC) module and the Phase Locked Loop (PLL) module, used in the Stop mode. By default, the SIM provides an extremely low power Stop mode (when OMR6_SD set to zero) by shutting down the PLL and, if possible, the oscillator master clock output. Optionally, (when OMR6_SD set to one) the SIM supports fast Stop mode recovery by leaving the PLL and oscillator output stage alone when entering the Stop mode.

Extreme low power Stop mode works as follows. Upon entering the Stop mode, the SIM asserts its PLL_SHUTDOWN output, causing the PLL to be disabled and bypassed. After one cycle, it asserts its OSC_LOPWR output, feeding the LOW_PWR_MODE input of OSC.

Power Mode Controls

When a fast Stop mode recovery is used (i.e. the OMR6_SD bit in the core is set), neither OSC_LOPWR nor PLL_SHUTDOWN will assert during the Stop mode entry. In this case, the Stop mode entry leaves the clock generation system alone. When there is a return to the Run mode, the clock (PLL based or direct) will be just as it was when Stop was entered. This consumes more power, but it avoids the delay associated with restarting the PLL and waiting for it to lock.

Note: The TAP must be reset (TRST set low) prior to the first functional reset of the part. The TAP reset musts be asserted at power-on for the POR reset to work correctly.

The SIM does not automatically restart or select the PLL upon recovery from Low Power mode. This choice is left to the applications software. Refer to the documentation of the oscillator module for details on its Low Power mode input.

Chapter 5

External Memory Interface (EMI)