Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

On-Chip Clock Synthesis Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

10.1.3 Prescaler

The prescaler is used when a higher frequency input clock or crystal (1 MHz or more) is required in an application. The prescaler provides a slower clock signal as input to the RTI and COP timer. In addition, this low-frequency clock signal can be used as input to the timers in the timer module. When a 32 kHz or 38.4 kHz crystal is used with the DSP56824, it is appropriate to set the prescaler to divide by one (effectively bypassing the prescaler).

The prescaler clock is generated by a divider clocked on the oscillator output. The following divide ratios are supported: /1, /16, /64, and /256. The prescaler can also be disabled. The divide ratio is determined by the value of the PS[2:0] bits in the PCR1. See Section 10.2.1.6, “Prescaler Divider (PS[2:0])—Bits 10–8,” for detailed information on PS bit values and corresponding divide rates.

NOTE:

The maximum frequency of the prescaler clock is limited to one-sixteenth of the maximum clocking frequency of the part. This means that for a 70 MHz DSP56824, the clocking frequency of the prescaler clock must be less than or equal to 4.375 MHz.

10.1.4 Clockout Multiplexer (MUX)

The clockout multiplexer (MUX) selects which clock is provided to the CLKO pin. Disable this pin for lowest power operation using the control bits in PCR1. For testing and some user applications, it is desirable to provide the Phi clock on this pin. In some cases, it may be desirable to provide the oscillator clock on the CLKO pin.

10.1.5 Control Registers

The PCR0 and PCR1 control registers provide the majority of the user control over the clock synthesis module. Individual bits and their functions are described in Section 10.2, “Clock Synthesis Programming Model.”

10.2 Clock Synthesis Programming Model

The clock synthesis module provides two control registers to manage the frequency, signal paths, and outputs of the DSP56824 clocks:

•PCR1—PLL control register 1

•PCR0—PLL control register 0

Clock signal control is also provided by additional registers within the following peripherals:

•Synchronous serial interface (SSI)

•Serial peripheral interface (SPI)

•COP/RTI

NOTE:

Clock signals used within the peripherals can be provided as clock outputs. Users should be reminded that changing a clock may change the behavior of another peripheral.

10-4 DSP56824 User’s Manual

For More Information On This Product,

Go to: www.freescale.com