Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

Synchronous Serial Interface

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

CLK

FS

STSR

TX

Data

STD

TDE

TUE

SRD

RX

Data

RDF

ROE

AA1441

Figure 8-14. Network Mode Timing—Continuous Clock

8.4.3 Gated Clock Operation

Gated clock mode is often used to hook up to SPI-type interfaces on microcontroller units (MCUs) or external peripheral chips. In gated clock mode, the presence of the clock indicates that valid data is on the STD or SRD pins. For this reason, no frame sync is needed in this mode. Once the transmission of data has completed, the clock pin is tri-stated. Gated clocks are allowed for both the transmit and receive sections with either an internal or external clock and in normal mode. Gated clocks are not allowed in network mode.

The clock runs when the TE bit, the RE bit, or both are appropriately enabled. For the case of an internally generated clock, all internal bit clocks, word clocks, and frame clocks continue to operate. When a valid time slot occurs (such as the first time slot in normal mode), the internal bit clock is enabled onto the

8-28 DSP56824 User’s Manual

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