BFSET

#$00F0,X:PCC

; Configure:

; MISO1, MOSI1, SCK1, ~SS1 for SPI slave

; (~SS0 required for slave mode)

; other pins remain as previously set

; (reset default is GPIO)

;

[PCDDR unused]

; SPI ensures correct direction of used SPI pins

BFCLR

#$1000,X:IPR

; Disable SPI1 interrupts

; (unnecessary; mentioned for completeness)

BFSET

#$0040,X:SPCR1

; (SPE) SPI Enabled.

;****************

;*

SPI0:

Master

*

;*

SPI1:

Slave

*

START

EQU

$0040

; Start of program

BCR

EQU

$FFF9

; Bus Control Register

IPR

EQU

$FFFB

; Interrupt Priority Register

PCC

EQU

$FFED

; Port C Control Register

PCDDR

EQU

$FFEE

; Port C Data Direction Register

PCR0

EQU

$FFF2

; PLL Control Register 0

PCR1

EQU

$FFF3

; PLL Control Register 1

SPCR0

EQU

$FFE2

; SPI0 Control Register

SPCR1

EQU

$FFE6

; SPI1 Control Register

SPDR0

EQU

$FFE0

; SPI0 Data Register

SPDR1

EQU

$FFE4

; SPI1 Data Register

SPSR0

EQU

$FFE1

; SPI0 Status Register

SPSR1

EQU

$FFE5

; SPI1 Status Register

;****************

;* Vector setup *

;****************

ORG

P:$0000

; Cold Boot

JMP

START

; also Hardware RESET vector (Mode 0, 1, 3)

ORG

P:$E000

; Warm Boot

JMP

START

; Hardware RESET vector (Mode 2)

;

ORG

P:$0028

;

;

JSR

; SPI1 Serial System vector [unused]

;

ORG

P:$002A

;

;

JSR

; SPI0 Serial System vector [unused]

ORG

P:START

; Start of program

;*****************

;* General setup *

;*****************

MOVEP

#$0000,X:BCR

; External Program memory has 0 wait states.

; External data memory has 0 wait states.

; Port A pins are tri-stated when no external

; access occurs.

MOVEP

#$0180,X:PCR1

;Configure:

;(PLLE) PLL disabled (bypassed)

; - Oscillator supplies Phi Clock.

;(PLLD) PLL Power Down disabled (PLL active)

; - PLL block active for PLL to attain lock.

;(LPST) Low Power Stop disabled.

;(PS[2:0]) Prescaler Clock disabled.

;(CS[1:0]) Clockout pin sends Phi Clock.

MOVEP

#$0260,X:PCR0

; Set Feedback Divider to 1/20.

; ...

; insert delay here: wait for PLL lock

; as specified in data sheet.

; ...

BFSET

#$4000,X:PCR1

; Enable PLL for Phi Clock.

;********************

;* SPI Master setup *

;********************

BFCLR

#$0040,X:SPCR0

; (SPE) SPI disabled.

MOVEP

#$0116,X:SPCR0

;Configure:

;(SPR[2:0]) SPI Clock Rate Select at /64.

;(SPIE) SPI Interrupt disabled.

;(WOM) Wired-OR Mode disabled:

; - push-pull drivers.

;(MST) Master mode selected.

;(CPL) serial Clock Polarity:

; - SCK pin idles as logic low.

;(CPH) Clock Phase protocol:

; - ~SS line is tied low if only one slave.

BFSET

#$0007,X:PCC

;Configure:

;MISO0, MOSI0, SCK0 for SPI master,

;~SS0 as PC3 for GPIO.

;Other pins remain as previously set

; (reset default is GPIO).

BFSET

#$0008,X:PCDDR

;Configure GPIO pin PC3 as output.

BFCLR

#$2000,X:IPR

;Disable SPI0 interrupts

; (unnecessary but here for completeness).

BFSET

#$0040,X:SPCR0

;(SPE) SPI Enabled.

;+----------------------------------------------------------------

+

MOVE

#$0000,X0

;Clear X0 to initialize output pattern

XLOOP ; Transfer Loop

MOVE

X0,A1

;Load output pattern into A1.

DO

#2,XFER

;Send two bytes (lower byte goes first).

JSR

TXBYTE

;Transmit byte out on MOSI0 line.

JSR

RXBYTE

;Receive byte in from MOSI1 line.

XFER

CMP

X0,B0

;Did the data come back all right?

BNE

XLOOP

;No, something is wrong with connection.

; --

Try again until successful.

INC

X0

;Increment X0 for next output pattern.

BRA

XLOOP

TXBYTE

;Transmit Byte

MOVEP

X:SPSR0,A0

;Read SPSR0 to clear SPIF so SPI can write

; to SPDR0, otherwise write is inhibited.

MOVEP

A1,X:SPDR0

;Transmit lower byte of data from A1.

REP

#8

;Shift upper byte of data for next transfer

ASR

A

; (only needed during first pass of loop).

RTSRXBYTE

;Receive Byte

BFTSTH

$0080,X:SPSR1

;Test for SPIF flag high in Slave

BCC

RXBYTE

;Wait until data ready to be received

MOVEP

X:SPSR1,B1

;Read SPSR1 to clear SPIF flag (for status)

MOVEP

X:SPDR1,B1

;Receive data into B1

REP

#8

;

ASR

B0

;Shift data into B0

RTS