Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

OnCE™ Module

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Figure 12-8. Debug Event Pin

12.4.4.5 FIFO Halt (FH)—Bit 7

The FIFO halt (FH) bit allows the user to halt address capture in the OnCE change-of-flow FIFO (OPFIFO) register, the OnCE PAB fetch register (OPABFR), the OnCE PAB decode register (OPABDR), and the OnCE PAB execute register (OPABER) when the bit is set. The FH bit is set only by writes to the OCR, never automatically by on-chip circuitry (that is, it is a control bit, never a status bit). This gives the user a simple method to halt the PAB history capture without setting up event conditions using the EM bits and breakpoint circuitry.

NOTE:

The FIFO is halted immediately after the FH bit is set. This means that the FIFO can be halted in the middle of instruction execution, leading to incoherent OPFIFO register contents.

12.4.4.6 Event Modifier (EM[1:0])—Bits 6–5

The event modifier (EM[1:0]) bits allow different actions to take place when a OnCE event occurs. OnCE events are defined to be occurrences of hardware breakpoints, software breakpoints, and traces. Each event occurrence sets the respective occurrence bit (HBO, SBO, or TO) in the OnCE status register (OSR), regardless of EM encoding. In addition, when the DE pin is enabled, each event occurrence drives DE low until the event is rearmed, again regardless of EM encoding.

The first trigger condition of a breakpoint sequence does not set a bit in the OSR. Only completion of the final trigger condition sets the respective bit in the OSR (hardware breakpoint occurrence, HBO, for all but one BK encoding).

When EM[1:0] = 00, a OnCE event halts the core and the chip enters debug mode. The core is halted on instruction boundaries only. When the core is halted, the user has access to core registers as well as data and program memory locations, including peripheral memory-mapped registers. The user also has the ability to execute core instructions forced into the instruction pipeline via OnCE module transfers.

If EM[1:0] = 01, the core does not halt when an event occurs (that is, debug mode is not entered), but the OPFIFO, OPABFR, OPABDR, and OPABER registers stop capturing. This allows the user to access the PAB history information while the application continues to execute.

If EM[1:0] = 10, the core does not halt when an event occurs, but a level 1 interrupt occurs with a vector at location P:$000C. This allows the user to execute diagnostic subroutines upon event occurrences or even to patch program memory by setting a breakpoint at the beginning of the code to be patched. Note that trace occurrences do not trigger vectored interrupts. Only hardware and software breakpoints are allowed OnCE events for this EM encoding.

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Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

Command, Status, and Control Registers

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

If EM[1:0] = 11, the core does not halt and no other action is taken other than the pulsing low of DE (when enabled). This encoding serves to produce an external trigger without changing OnCE module or core operation.

EM encodings 11 and 10 enable automatic event rearming. This means that 8 Phi clock cycles after the event occurrence flag (HBO, TO, or SBO) is set, it is reset, thus rearming the event. If DE is enabled, it is asserted (driven low) for 8 Phi clock cycles, and then released. If another event occurs within those 8 Phi clock cycles or directly after, the occurrence flag is set immediately and DE remains low.

To rearm an event in EM encoding 00, debug mode must be exited (typically by executing a core instruction when setting EX and GO in the OCMDR), thereby clearing the status bits and releasing DE.

To rearm an event in EM encoding 10, the OCR must be written. If the user does not wish to change the value of OCR, writing OCR with its current value rearms the event successfully. DE, if enabled, is released when this occurs.

Enabling trace for EM = 11 or EM = 10 is not particularly useful. Since a trace event occurs on every instruction execution once OCNTR reaches zero, the event is continuously set, meaning that DE stays low after the first event. For EM = 10, vectoring is disabled on trace occurrences, though DE goes low and stays low after the first trace occurrence. The appropriate event occurrence bit is not reset in this case (tracing and OCNTR = $0000) until trace mode is disabled and an event-clearing action takes place, such as exiting debug mode or writing the OCR while in user mode.

NOTE:

Any OCR write in user mode resets the event flags, while OCR writes in debug mode do not reset the event flags.

Table 12-9 on page 12-17 summarizes the different EM encodings.

When events are rearmed, OCNTR is not reloaded with its original value.

It remains at zero, and the next triggering condition generates an event.

Care must be taken when changing the EM bits. It is recommended that the particular event (trace, hardware, or software breakpoint) is disabled first. On the next OCR write, the EM bits can be modified and the event reenabled. This is only required when the chip is not in debug mode. Improper operation can occur if this is not followed. For example, if the FIFO has halted due to an event occurrence with EM[1:0] = 01 and the next OCR write changes EM[1:0] to 00, the chip enters debug mode immediately. Automatic rearming is desirable if the 10 encoding is being used for a ROM patch or the 11 encoding is