Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Freescale Semiconductor, Inc.

OnCE™ Module

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005

Figure 12-8 on page 12-16 shows the internal configuration of the TRST/DE pin. The open-drain output function indicates that a OnCE event has occurred. For example, a trace or breakpoint occurrence causes the pin to go low for a minimum of 8 Phi clocks. This pin is further described in Section 12.4.4.6, “Event Modifier (EM[1:0])—Bits 6–5.”

When the JTAG IR does not contain an ENABLE_ONCE instruction, the OCR control bits are reset only by assertion of RESET or COP timer reset. If the ENABLE_ONCE instruction is in the JTAG IR at the time of reset, the OCR bits are not modified.

NOTE:

Although this implementation is not in strict accordance with IEEE 1149.1a-1993, a JTAG user can confidently use this pin in its TRST mode by ensuring that RESET is asserted on power up. Setting OCR[14] requires a very specific and lengthy JTAG sequence. OCR[14] cannot be set by any other sequence. Similarly, to guarantee full hardware reset, both RESET and TRST should be asserted.

12.3 OnCE Module Architecture

While the JTAG port described in Section 13.2, “JTAG Port Architecture,” on page 13-2 provides board test capability, the OnCE module provides emulation and debug capability to the user. The OnCE module permits full-speed, non-intrusive emulation on a user’s target system or on a Motorola Application Development Module (ADM) board.

A typical debug environment consists of a target system where the DSP resides in the user-defined hardware. The DSP’s JTAG port interfaces to a command converter board over a seven-wire link, consisting of the five JTAG serial lines, a ground, and reset wire. The reset wire is optional and is only used to reset the DSP and its associated circuitry. Refer to your development system’s documentation for information on debugging using the JTAG port interface.

The OnCE module is composed of four different sub-blocks, each of which performs a different task:

•Command, status, and control

•Breakpoint and trace

•Pipeline registers

•FIFO history buffer

12.3.1 OnCE Port Block Diagram

A block diagram of the OnCE module is shown in Figure 12-2 on page 12-5. Information is shifted serially in and out of the OnCE port logic via the TDI and TDO signals. Typically the source and destination of this information is one or more OnCE port registers. An overview of the registers is given in the following section.

Freescale Semiconductor, Inc.

ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005