Chapter 11

COP and RTI Module

This section describes the Computer Operating Properly (COP) and real-time interrupt (RTI) module (COP/RTI) provided on the DSP56824.

The COP/RTI module provides two separate functions: a watchdog-like timer and a periodic interrupt generator. The COP timer guards processor activity and provides an automatic reset signal if a failure occurs. Both functions are contained in the same block because the input clock for both comes from a common clock divider.

11.1 COP and Real-Time Timer Architecture

The COP timer protects against system failures by providing a means to escape from unexpected input conditions, external events, or programming errors. Once started, the COP timer must be reset by software on a regular basis so that it never reaches its time-out value. When the COP timer reaches its time-out value, an internal reset is generated within the chip and the COP reset vector is fetched. It is assumed that if the COP reset is not received from the program, a system failure has occurred.

The COP functionality is typically used by software to ensure that the chip is operating properly. Software must periodically service the COP timer by correctly writing to the COP reset (COPRST) register before the COP timer times out. The COP timer has its own reset vector. This allows the reset recovery from a COP time-out to differ from the reset procedure done after a hardware reset.

A COP reset is very similar to a hardware reset through the RESET pin. The minor differences are the address from which the reset vector is fetched and the length of the period during which reset is asserted.

The RTI capability provides a periodic interrupt in an application. It consists of a long decrementing counter chain that runs continuously when enabled. When it reaches zero, a status flag is set and an interrupt is generated (optionally, when enabled by the user). The RTI has its own interrupt vector location to reduce overhead in interrupt servicing.

Figure 11-1 on page 11-2 shows a block diagram of the COP/RTI timer module. This module contains a programmable divider chain for dividing the prescaler clock to a periodic rate that can be used as an RTI. This real-time clock is further divided down to get a COP timer reset. The COP and RTI control (COPCTL) register is used to set up the peripheral and program the divide ratios.

COP and RTI Module

Figure 11-1. RTI and COP Timer Block Diagram

NOTE:

The maximum frequency of the prescaler clock is limited to one-sixteenth of the maximum clocking frequency of the part. This means that for a 70 MHz DSP56824, the clocking frequency of the prescaler clock must be less than or equal to 4.375 MHz.

The RTI timer and the COP timer share the scaler (SC), real-time prescaler (RP), and COP/RTI divider (DV) dividers in the clock divider chain. The current value of the RTI timer can be determined at any time by reading the COP/RTI count (COPCNT) register, the bits of which reflect the shared components of the COP/RTI divider chain. These shared components comprise the RTI timer.

The COP timer is a timer whose clock source is cascaded from the RTI timer. It consists of the COP timer (CT) divider. The COP timer counts from either 7 or 63 down to 0, and then provides the COP reset signal, which resets the DSP chip. The COP timer cannot be read. Its only function is to count down to 0 and send a COP reset signal, unless the COP timer itself is reset. The COP reset sequence, provided in Example 11-1 on page 11-9, must be programmed to run periodically. Sending this reset sequence is analogous to renewing a library book before it is due.

The COPCTL register reflects the control status of both the RTI timer and the COP timer. The COP/RTI peripheral is enabled by the RTI enable (RTE) bit in the COPCTL register. In addition, the On-Chip Emulation (OnCE™ ) module within the DSP56800 core can disable the counting in the RTI and COP timers to prevent counting when the chip is no longer executing instructions, but instead is in debug mode. This is useful for debugging real-time systems.

When the COP timer expires and a COP reset occurs, the following sequence takes place:

1.DSP reset occurs.

2.The original MODA and MODB values that were captured on RESET deassertion are reloaded into the MA and MB bits of the OMR.

3.Program control is transferred to the appropriate COP reset vector determined by the values in MA and MB.

MODA, MODB, and XCOLF are not resampled on COP reset.