PLL Module Low-Power Operation

10.4.3 Turning Off the PLL Before Entering Stop Mode

To turn off the PLL before entering stop mode, execute the following sequence before issuing the STOP instruction:

1.Clear the PLLE bit to switch back to the oscillator clock.

2.Set the PLLD bit to one to power down the PLL.

3.Execute the STOP instruction.

NOTE:

The PLL can be left running when entering stop mode. This allows a faster exit to normal mode. There is no wait for PLL lock because the PLL continues to run in stop mode.

10.5 PLL Module Low-Power Operation

In applications requiring minimum power consumption, there are several options for lowering the power consumption of the chip within the clock synthesis module in stop or wait mode. These are discussed individually below.

10.5.1 Turning Off the Entire Clock Synthesis Module

If no internal clocks are required by an application in stop mode, shut off the entire module for lowest power consumption. This is done by resetting the PLLD bit to 1 (PLLE must already be cleared), setting the PS[2:0] bits (in the PCR1) to 001, setting the CS[1:0] bits (in the PCR1) to 11, and setting the LPST bit (in the PCR1) to 1. See Section 10.2.1, “PLL Control Register 1 (PCR1),” for details on the PCR1.

When the LPST bit is set to 1, an additional period of time is required for crystal oscillator stabilization. Upon exiting stop mode, it is necessary to wait for the PLL to stabilize again (relock). Both these times are specified in the DSP56824 Technical Data Sheet.

10.5.2 Turning Off the Prescaler Divider When Not in Use

For applications not requiring a prescaler clock to any peripherals, turn off the prescaler divider by setting the PS[2:0] bits in PCR1 to 001.

NOTE:

The prescaler divider can be turned off independently from the PLL or

CLKO pin.

On-Chip Clock Synthesis

10.5.3 Turning Off the PLL When Not in Use

For applications in which the time required for the PLL to relock when exiting stop mode is not an issue, the PLL can be turned off by setting the PLLD bit in the PCR1 to one. (See Section 10.2.1, “PLL Control Register 1 (PCR1),” on page 10-5.) This can be done only after the PLLE bit in PCR1 has been cleared.

NOTE:

The PLL can be turned off independently from the prescaler divider or CLKO pin. Upon exiting stop mode, the PLL must be reenabled and it is necessary to wait for the PLL to stabilize again (relock).

10.5.4 Turning Off the CLKO Pin When Not in Use

For applications where no external clockout pin is required, it is recommended to turn off the CLKO pin to lower power and reduce switching on the pins. This can be accomplished by setting the CS[1:0] bits to 11. See Section 10.2.1, “PLL Control Register 1 (PCR1).”

NOTE:

The CLKO pin can be turned off independently from the PLL or prescaler divider.