PLL Lock

10.3.5 Everything Disabled

In this stop mode, the DSP56800 core and the COP/RTI, PLL, SPI, SSI, and timer-module peripherals are placed in low-power stop mode where all clocks are gated off. The PLL loses lock in this condition. The CLKO pin is disabled and the oscillator is disabled as well. If an external crystal is used, the processor must wait for the crystal to stabilize before exiting stop mode. It may also be necessary to wait for the PLL to relock.

This mode is entered by executing a STOP instruction when the LPST bit in the PCR1 is set. This is the lowest power stop mode available.

10.4 PLL Lock

There are several conditions when it is necessary to wait for the PLL to lock:

•When the chip first powers up

•When the PLL is taken out of its power-down state (clearing the PLLD bit when it had previously been set)

•When the frequency of the PLL is changed by modifying the YD bits in the PCR0

NOTE:

Changing the PLL frequency may require changing external filter components and is not recommended. See the DSP56824 Technical Data Sheet for more information.

In each of these cases, it is necessary to wait until the PLL locks on its final frequency before the PLL clock is sent to the DSP56800 core and the peripherals (PLLE = 1). PLL lock time is provided in the DSP56824 Technical Data Sheet. Failure to wait until the PLL locks can result in improper processing states, software errors, and other problems.