Low-Power Wait and Stop Modes

10.2.2.2 Feedback Divider (YD[9:0])—Bits 14–5

The feedback divider (YD[9:0]) bits control the down counter in the feedback loop, causing it to divide by the value YD + 1, where YD is the value contained in the YD[9:0] bits. The YD[9:0] bits are cleared on DSP reset.

The resulting Phi clock signal must be within the limits specified in the “Specifications” section of the DSP56824 Technical Data Sheet. The frequency of the VCO should also remain higher than the specified minimum value. Recommended PLL MFs for the DSP56824 are also provided in the DSP56824 Technical Data Sheet.

10.2.2.3 Reserved Bits—Bits 4–0

Bits 4–0 are reserved and are read as zero during read operations. These bits should be written with zero to ensure future compatibility.

10.3 Low-Power Wait and Stop Modes

The DSP56824 can be configured for very low-power consumption in wait mode or minimal power consumption in stop mode, based on application needs. In wait mode, all internal core clocks are gated off, but the Phi clock continues to operate so that peripherals continue to function and can bring the chip out of wait mode by using a peripheral interrupt. In stop mode, the Phi clock and all internal core clocks are gated off. Stop mode uses less power than wait mode. Before entering either stop or wait mode, it is possible to enable or disable the following blocks individually:

•CLKO pin

•PLL module

•COP/RTI module

•Timer module

•SPI module

•SSI module

In addition, it is also possible to disable the prescaler block, but this in turn disables the COP/RTI and the timer module blocks. All blocks left enabled continue to run in stop mode, except the SPI and SSI. The timer module and COP/RTI can bring the chip out of stop mode. The SPI and SSI are always powered down in stop mode.

Several options for the clock synthesis block are available to the user in stop mode.

•Leave PLL enabled—low power, short wake-up time since PLL already stabilized

•Disable PLL—lower power, long wake-up time for PLL to stabilize

•Leave prescaler enabled—allows COP and real-time timers to continue operating

•Disable prescaler—lower power, disables clock to COP and real-time timers

•Disable oscillator—lowest power, all internal clocks disabled, longest wake-up time

Leaving the PLL enabled in stop or wait mode avoids the need to wait for the PLL to relock upon exiting. Examples of low-power configurations in stop mode follow in Section 10.3.1, “PLL, COP, Real-Time Clock, Timers, and CLKO Enabled,” through Section 10.3.5, “Everything Disabled.”

On-Chip Clock Synthesis

10.3.1 PLL, COP, Real-Time Clock, Timers, and CLKO

Enabled

In this stop mode, the DSP56800 core and the SPI and SSI peripherals are placed in low-power stop mode, in which all clocks are gated off. The PLL remains running and locked, the COP and real-time clock timers can still continue functioning, and a clock waveform can be provided on the CLKO pin, if desired. In this mode the oscillator is still running.

NOTE:

It is also possible to leave the timer module running if clocked with the prescaler clock. This stop mode consumes the most power.

This mode is entered by executing a STOP instruction with the PLL, COP/RTI, and timer module peripherals still enabled. The timer module must be clocked with the prescaler clock.

NOTE:

The CLKO pin can be disabled independently using the CS[1:0] control bits in the PCR1, described in Section 10.2.1.7, “CLKO Select (CS[1:0])—Bits 7–6.”

10.3.2 COP, Realtime Clock and CLKO Pin Enabled

In this stop mode, the DSP56800 core and the PLL, SPI, SSI, and timer-module peripherals are placed in low-power stop mode where all clocks are gated off. The PLL loses lock in this condition. The COP and real-time clock timers can still continue functioning, and a clock waveform can be provided on the CLKO pin, if desired. In this mode the oscillator is still running.

This mode is entered by executing a STOP instruction with the PLL disabled and the COP/RTI peripheral still enabled. The CLKO pin can also be disabled independently using the CS[1:0] control bits in the PCR1.

10.3.3 PLL and CLKO Pin Enabled

In this stop mode, the DSP56800 core and the COP/RTI, SPI, SSI, and timer-module peripherals are placed in low-power stop mode where all clocks are gated off. The PLL remains locked and running in this condition. A clock waveform can be provided on the CLKO pin, if desired. In this mode the oscillator is still running.

This mode is entered by executing a STOP instruction with the PLL enabled and the COP/RTI peripheral disabled. The CLKO pin can also be disabled independently using the CS[1:0] control bits in the PCR1.

10.3.4 CLKO Pin Enabled

In this stop mode, the DSP56800 core and the COP/RTI, PLL, SPI, SSI, and timer-module peripherals are placed in low-power stop mode where all clocks are gated off. The PLL loses lock in this condition. A clock waveform is provided on the CLKO pin. In this mode the oscillator is still running. It may be necessary to wait for the PLL to relock after exiting stop mode.

This mode is entered by executing a STOP instruction when the PLL and COP/RTI peripherals are both disabled and the CLKO pin is enabled.