NOTE:

The maximum frequency of the prescaler clock is limited to one-sixteenth of the maximum clocking frequency of the part. This means that for a 70 MHz DSP56824, the clocking frequency of the prescaler clock must be less than or equal to 4.375 MHz.

Changing the prescaler control bits when the COP timer is enabled via the CPE bit (in the COPCTL register) does not result in a change of the prescaler divider. This prevents an application from accidentally disabling the COP timer by disabling the prescaler clock. If the COP enable (CPE) bit is set, then the PS bits can still be written, but the prescaler division ratio is not changed. See Section 11.2.1, “COP and RTI Control Register (COPCTL),” on page 11-4 for a description of the COPCTL register.

NOTE:

There is a restriction when setting the prescaler’s division ratio. The case where the prescaler is set to divide by one and the PLL is set for an MF of one when the PLL provides the Phi clock (PLLE = 1) is not allowed. Violating this restriction results in faulty prescaler clock synchronization in the peripherals.

10.2.1.7 CLKO Select (CS[1:0])—Bits 7–6

When programmed in conjunction with the TSTEN bit, the CLKO select (CS[1:0]) control bits are used to enable one of three different clocks to the CLKO pin or to disable all clocks to this pin. After DSP reset, the Phi clock output is provided on the CLKO pin. The other options are presented in Table 10-3. The CS[1:0] bits are cleared on DSP reset.

Table 10-3. CLKOUT Pin Control