Clock Synthesis Programming Model

The clock synthesis programming model is shown in Figure 10-3 on page 10-5.

Figure 10-3. Clock Synthesis Programming Model

10.2.1 PLL Control Register 1 (PCR1)

The PLL control register 1 (PCR1) is a 16-bit read/write register used to direct the operation of the on-chip clock synthesizer. The PCR1 control bits are defined in Section 10.2.1.1, “Reserved Bit—Bit 15,” through Section 10.2.1.10, “Reserved Bits—Bits 2–0.”

10.2.1.1 Reserved Bit—Bit 15

Bit 15 is reserved and is read as zero during read operations. This bit should be written with zero to ensure future compatibility.

10.2.1.2 PLL Enable (PLLE)—Bit 14

The PLL enable (PLLE) control bit and the PLLD control bit (bit 13) interact to control PLL operation. When PLLE is set, the DSP56824 system clock (Phi clock) is generated by the on-chip PLL, using the YD bits to select the PLL multiplication factor (MF).

The state of the PLL is defined by the PLLD control bit (bit 13). The interaction of PLLE and PLLD is shown in Table 10-1 on page 10-6.

10.2.1.3 PLL Power Down (PLLD)—Bit 13

The state of the PLL is defined by the PLL power down (PLLD) control bit (bit 13). The PLLE and PLLD bits work together to control PLL operation, as shown in Table 10-1 on page 10-6. When the PLLE bit is set, the DSP56824 system clock (Phi clock) is generated by the on-chip PLL.

When the PLLD bit is set, the PLL is in the power down mode, a low-current mode in which the VCO is inactive. When the PLLD bit is cleared, the PLL is in the active mode. Before turning the PLL off, clear the PLLE bit to bypass the PLL. Then put the PLL in power down mode by setting the PLLD bit. Setting the PLLD bit powers down the complete PLL block, including the PS and YD registers, described in Section 10.2.1.6, “Prescaler Divider (PS[2:0])—Bits 10–8,” and Section 10.2.2.2, “Feedback Divider (YD[9:0])—Bits 14–5,” respectively.