Timing System Architecture

The two control registers PCR0 and PCR1 control PLL multiplication, powering down, and MUX selects as well as other PLL-related options.

10.1.1 Oscillator

The DSP56824 supports frequencies from 32 kHz to the maximum specified frequency of the chip. The oscillator derives a clock signal from an external crystal. It is also possible to input an external clock directly to the EXTAL pin. In this case, no crystal is used and the XTAL pin can be left floating. The output of the oscillator drives the prescaler and the PLL inputs. This output also can provide an input for the clockout MUX. Detailed information and design guidelines are furnished in the DSP56824 Technical Data Sheet.

10.1.2 Phase Lock Loop (PLL)

The PLL is used to multiply up the oscillator clock frequency to the frequency needed by the core and peripherals for operation. For basic operation, the PCR1 is configured with the PLL power down (PLLD) bit cleared and the PLLE bit set to 1. When the PLLD bit is cleared, the PLL loop is powered on, and the oscillator clock is multiplied by the value of the bits in YD[9:0] + 1 at the voltage controlled oscillator (VCO). (The YD bits are contained in the PCR0.) When the PLL enable (PLLE) bit is set to one, the output of the VCO drives the Phi clock.

By setting the PLLE bit to zero, the PLL is bypassed and the Phi clock is driven directly by the oscillator clock. The bits in PCR0 and PCR1 are described in Section 10.2, “Clock Synthesis Programming Model.” Figure 10-2 shows a block diagram of the PLL.

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AA1442

Figure 10-2. PLL Block Diagram