Chapter 10

On-Chip Clock Synthesis

The clock synthesis module generates the clocking for the DSP56824. This section describes the module’s architecture, programming model, and different low-power modes of operation. The module generates three clock signals for use by the DSP56800 core and DSP56824 peripherals. It also contains a phase lock loop (PLL) that can multiply the frequency, as well as a prescaler divider used to distribute lower-frequency clocks to peripherals, leading to lower power consumption on the chip. It also selects which clock, if any, is routed to the clock output (CLKO) pin of the DSP56824.

10.1 Timing System Architecture

The DSP56824 timing system, shown in Figure 10-1 on page 10-2, has the clock synthesis module at its core. This module is composed of the following five blocks:

•Oscillator

•Phase lock loop (PLL)

•Prescaler

•Clockout multiplexer (MUX)

•Control registers

Together, these five blocks generate the following three clock signals used for core and peripheral operation:

•Oscillator clock

•Phi clock

•Prescaler clock

On-Chip Clock Synthesis

Figure 10-1. DSP56824 Timing System

Typically, the oscillator is attached to an external crystal. It can also be driven by an external oscillator. The output of the oscillator, called the oscillator clock signal, is provided to the prescaler, the PLL blocks, and the CLKOUT MUX.

The prescaler divides the oscillator clock signal and provides it to the Computer Operating Properly and real-time interrupt (COP/RTI) module, discussed in Chapter 11, “COP and RTI Module,” to the general-purpose timer module, and to the clockout MUX. This signal is called the prescaler clock.

The PLL multiplies up the oscillator clock signal and provides it to the DSP56800 core, to the SSI, to the SPI modules, to the general-purpose timer module, and to the clockout MUX. This multiplied signal is called the Phi clock.

The clockout MUX delivers one of these three signals (or none) to the CLKO pin.