Timer Interrupt Priorities
9.3 Timer Interrupt Priorities
The timer module has a simple interrupt-priority scheme among its different timers, as shown in Table 9-7. It is important to service timer interrupts with higher priorities in a timely fashion to determine if any timer interrupts with a lower priority are also present.
Table 9-7. Timer Interrupt Priorities
Timer |
Priority |
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0 |
Highest |
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1 |
Middle |
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2 |
Lowest |
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9.4 Event Counting with the Timer Module
This section contains examples of how to program some of the timing and counting capabilities of the general-purpose timers. This set of examples is by no means a complete list of either the capabilities or the programming techniques that can be used. Instead, it offers a representative range of what can be accomplished. The timer module can be used as an event counter. Setting the ES bits to 11 configures the timer to count the number of edges (external events) detected on the specified TIO pin. An external event is defined as a rising edge when the INV bit is cleared or as a falling edge when the INV bit is set. After the pin is conditionally inverted, it is synchronized to the Phi clock. Events on the TIO pin can be counted in wait mode, but cannot be counted in stop mode.
NOTE:
The maximum allowed frequency on the TIO pin is the frequency of the
Phi clock divided by four.
Timers 9-9
Timers
Example 9-1 shows how to count events on a pin.
Example 9-1. Counting Events on a Pin
;******************************************************** ;* Example of Counting Events on a pin (with interrupt) *
;* for Timer Module |
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* |
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;* of DSP56824 chip |
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* |
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;******************************************************** |
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START |
EQU |
$0040 |
; Start of program |
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BCR |
EQU |
$FFF9 |
; Bus Control Register |
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IPR |
EQU |
$FFFB |
; Interrupt Priority Register |
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TCR01 |
EQU |
$FFDF |
; Timer 0 & 1 Control Register |
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TCR2 |
EQU |
$FFDA |
; Timer 2 Control Register |
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TCT0 |
EQU |
$FFDD |
; Timer 0 Count Register |
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TPR0 |
EQU |
$FFDE |
; Timer 0 Preload Register |
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;************** |
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;* Vector setup* |
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;************** |
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ORG |
P:$0000 |
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;Cold Boot |
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JMP |
START |
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;also Hardware RESET vector (Mode 0, 1, 3) |
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ORG |
P:$E000 |
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;Warm Boot |
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JMP |
START |
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;Hardware RESET vector (Mode 2) |
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ORG |
P:$0018 |
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; |
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JSR |
TISR |
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;Timer 0 Overflow vector |
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ORG |
P:START |
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;Start of program |
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;************** |
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;* General setup* |
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;************** |
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MOVEP |
#$0000,X:BCR |
;External Program memory has 0 wait states. |
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;External data memory has 0 wait states. |
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;Port A pins tri-stated when no external |
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; access. |
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BFCLR |
#$0200,SR |
;Allow IPL (Interrupt Priority Level) 0 |
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; -- Enable maskable interrupts. |
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;********************* |
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; -- (peripherals, and so on) |
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;* Timer Module setup* |
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;********************* |
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MOVEP |
#$0013,X:TCR01 |
;Configure: |
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;Timer 0 & 1 disabled. |
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;Timer 0 |
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; - don’t Invert input: detect rising edges |
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; - Overflow Interrupt enabled |
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; - TIO pin configured as input |
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; - timer clock Event source is TIO pin |
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MOVEP |
#$0000,X:TCR2 |
;Timer 2 disabled |
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MOVEP |
#234,X:TCT0 |
;Set Timer 0 Count Register to 234--235 events |
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MOVEP |
#234,X:TPR0 |
;Set Timer 0 Preload Register to 234. |
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BFSET |
#$0800,X:IPR |
;Enable timer module interrupts. |
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; ... |
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BFSET |
#$0080,X:TCR01 |
;Enable Timer 0 |
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;************** |
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;* Main routine* |
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;************** |
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TEST |
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;Test Loop |
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BRA |
TEST |
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; ... |
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TISR |
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;Timer Interrupt Service Routine |
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RTI |
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; interrupt code |
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9-10 |
DSP56824 User’s Manual |
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Event Counting with the Timer Module
A timer can also be used to decrement to zero and generate an interrupt, as shown in Example 9-2.
Example 9-2. Decrementing to Zero and Generating an Interrupt
;********************* ;* INTERRUPT example * ;* for Timer Module * ;* of DSP56824 chip *
;********************* |
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START |
EQU |
$0040 |
; Start of program |
BCR |
EQU |
$FFF9 |
; Bus Control Register |
IPR |
EQU |
$FFFB |
; Interrupt Priority Register |
PCR0 |
EQU |
$FFF2 |
; PLL Control Register 0 |
PCR1 |
EQU |
$FFF3 |
; PLL Control Register 1 |
TCR01 |
EQU |
$FFDF |
; Timer 0 & 1 Control Register |
TCR2 |
EQU |
$FFDA |
; Timer 2 Control Register |
TCT0 |
EQU |
$FFDD |
; Timer 0 Count Register |
TPR0 |
EQU |
$FFDE |
; Timer 0 Preload Register |
;**************** |
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;* Vector setup * |
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;**************** |
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ORG |
P:$0000 |
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; Cold Boot |
JMP |
START |
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; also Hardware RESET vector (Mode 0, 1, 3) |
ORG |
P:$E000 |
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; Warm Boot |
JMP |
START |
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; Hardware RESET vector (Mode 2) |
ORG |
P:$0018 |
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; |
JSR |
TISR |
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; Timer 0 Overflow vector |
ORG |
P:START |
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; Start of program |
;***************** |
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;* General setup * |
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;***************** |
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MOVEP |
#$0000,X:BCR |
; External Program memory has 0 wait states. |
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; External data memory has 0 wait states. |
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; Port A pins tri-stated when no external access |
BFCLR |
#$0200,SR |
; Allow IPL (Interrupt Priority Level) 0 |
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; -- Enable maskable interrupts. |
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; -- (peripherals, and so on) |
;***************************
;* PLL setup |
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* |
;* (to increase Phi Clock) * |
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;*************************** |
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MOVEP |
#$0180,X:PCR1 |
; Configure: |
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; (PLLE) PLL disabled (bypassed) |
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; -- Oscillator supplies Phi Clock |
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; (PLLD) PLL Power Down disabled (PLL active) |
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; -- PLL block active for PLL to attain lock |
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; (LPST) Low Power Stop disabled |
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; (PS[2:0]) Prescaler Clock disabled |
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; Select Phi Clock for Clockout pin (CLKO) |
MOVEP |
#$0260,X:PCR0 |
; Set Feedback Divider to 1/20 |
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; ... |
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; insert delay here: wait for PLL lock |
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; as specified in data sheet |
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; ... |
BFSET |
#$4000,X:PCR1 |
; Enable PLL for Phi Clock. |
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Timers |
9-11 |
Timers
Example 9-2. Decrementing to Zero and Generating an Interrupt (Continued)
;********************** |
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;* Timer Module setup * |
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;********************** |
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MOVEP |
#$001C,X:TCR01 |
; Configure: |
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; Timer 0 & 1 disabled |
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; Timer 0 |
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; -- don’t Invert TIO input: detect rising edges |
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; (irrelevant but mentioned for completeness) |
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; -- Overflow Interrupt enabled |
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; -- Timer Output toggles TIO pin on overflow |
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; -- timer clock Event source is Phi Clock /4 |
MOVEP |
#$0000,X:TCR2 |
; Timer 2 disabled |
MOVEP |
#99,X:TCT0 |
; Set Timer 0 Count Register to 99 (100 events). |
MOVEP |
#99,X:TPR0 |
; Set Timer 0 Preload Register to 99. |
BFSET |
#$0800,X:IPR |
; Enable Timer Module interrupts. |
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; ... |
BFSET |
#$0080,X:TCR01 |
; Enable Timer 0 |
;**************** |
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;* Main routine * |
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;**************** |
; ... |
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TEST |
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; Test Loop |
BRA |
TEST |
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TISR |
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; Timer Interrupt Service Routine |
RTI |
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; interrupt code |
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9-12 |
DSP56824 User’s Manual |
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Event Counting with the Timer Module
Example 9-3 shows how to program Timer 0 and Timer 1 to generate a timing signal with a 25 percent duty cycle.
Example 9-3. Timer Using 25% Duty Cycle
;************************** |
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;* 25% duty cycle example * |
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;* for Timer Module* |
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;* of DSP56824 chip |
* |
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;************************** |
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START |
|
EQU |
$0040 |
; Start of program |
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BCR |
|
EQU |
$FFF9 |
; Bus Control Register |
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IPR |
|
EQU |
$FFFB |
; Interrupt Priority Register |
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PCR0 |
|
EQU |
$FFF2 |
; PLL Control Register 0 |
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PCR1 |
|
EQU |
$FFF3 |
; PLL Control Register 1 |
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TCR01 |
|
EQU |
$FFDF |
; Timer 0 & 1 Control Register |
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TCR2 |
|
EQU |
$FFDA |
; Timer 2 Control Register |
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TCT0 |
|
EQU |
$FFDD |
; Timer 0 Count Register |
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TCT1 |
|
EQU |
$FFDB |
; Timer 1 Count Register |
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TPR0 |
|
EQU |
$FFDE |
; Timer 0 Preload Register |
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TPR1 |
|
EQU |
$FFDC |
; Timer 1 Preload Register |
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;**************** |
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;* Vector setup * |
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;**************** |
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;+----------------------------------------------------------------------- |
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+ |
;| Note: Bootstrap ROM configures OMR (Operating Mode Register) to set |
| |
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;| |
chip operating mode for Mode 2 (Normal Expanded Mode), then |
| |
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;| |
jumps to first location of internal program RAM (P:$0000). |
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;+----------------------------------------------------------------------- |
ORG |
P:$0000 |
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; Cold Boot |
+ |
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JMP |
START |
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; also Hardware RESET vector (Mode 0, 1, 3) |
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ORG |
P:$E000 |
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; Warm Boot |
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JMP |
START |
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; Hardware RESET vector (Mode 2) |
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ORG |
P:START |
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; Start of program |
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;***************** |
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||
;* General setup * |
|
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||
;***************** |
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||
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MOVEP |
#$0000,X:BCR |
; External Program memory has 0 wait states. |
||
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|
|
; External data memory has 0 wait states. |
|
|
|
|
|
; Port A pins tri-stated when no external access. |
|
;*************************** |
|
||||
;* PLL setup |
|
|
* |
|
|
;* (to increase Phi Clock) * |
|
||||
;*************************** |
|
||||
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MOVEP |
#$0180,X:PCR1 |
; Configure: |
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; (PLLE) PLL disabled (bypassed) |
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|
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; -- Oscillator supplies Phi Clock |
|
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|
|
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; (PLLD) PLL Power Down disabled (PLL active) |
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; -- PLL block active for PLL to attain lock |
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; (LPST) Low Power Stop disabled |
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; (PS[2:0]) Prescaler Clock disabled |
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; Select Phi Clock for Clockout pin (CLKO). |
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MOVEP |
#$0260,X:PCR0 |
; Set Feedback Divider to 1/20. |
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; ... |
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; insert delay here: wait for PLL lock |
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; as specified in data sheet |
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; ... |
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BFSET |
#$4000,X:PCR1 |
; Enable PLL for Phi Clock. |
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Timers |
9-13 |