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DSP56824 Overview

Table 1-1. DSP56800 Address and Data Buses (Continued)

Bus

Bus Name

Bus Width, Direction, and Use

 

 

 

 

 

 

PDB

Program data bus

16-bit, bidirectional, instruction word fetches

 

 

 

PGDB

Peripheral global data bus

16-bit, bidirectional, internal data movement

 

 

 

XDB2

X data bus 2

16-bit, unidirectional, internal data movement

 

 

 

EDB

External data bus

16-bit, bidirectional, external data movement

 

 

 

1.2.6 On-Chip Emulation (OnCE) Module

The On-Chip Emulation (OnCE) module allows the user to interact in a debug environment with the DSP56800 core and its peripherals non-intrusively. Its capabilities include examining registers, memory, or on-chip peripherals; setting breakpoints in memory; and stepping or tracing instructions. It provides simple, inexpensive, and speed-independent access to the DSP56800 core for sophisticated debugging and economical system development. The JTAG port allows access to the OnCE module and through the DSP56824 to its target system, retaining debug control without sacrificing other user-accessible on-chip resources. This capability eliminates the costly cabling and the access to processor pins required by traditional emulator systems. The OnCE interface is fully described in Chapter 12, “OnCE™ Module.”

1.3 DSP56800 Programming Model

The programming model for the registers in the DSP56800 core is shown in Figure 1-4 on page 1-11.

1-10

DSP56824 User’s Manual

 

DSP56800 Programming Model

Data Arithmetic Logic Unit

 

 

 

 

 

 

Data ALU Input Registers

 

 

 

 

 

 

 

 

 

 

 

31

 

16

15

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

X0

 

 

 

 

Y

 

Y1

 

 

Y0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

15

 

0

 

 

 

 

15

 

0

15

0

 

 

 

 

 

 

Accumulator Registers

 

 

 

 

35

32 31

 

16

15

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

A2

 

 

 

 

A1

 

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

0

15

 

0 15

 

 

0

 

35

32 31

 

16

15

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

B

 

B2

 

 

 

 

B1

 

B0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

0

15

 

0 15

 

 

0

 

Address Generation Unit

15

0

 

15

0

15

0

 

R0

 

 

N

 

 

M01

 

 

 

 

 

 

 

 

 

 

 

R1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pointer

 

Offset

 

 

Modifier

 

Registers

 

Register

 

 

Register

Program Controller Unit

15

0

15

8

7

0

15

 

0

 

 

PC

 

 

MR

 

CCR

 

 

 

OMR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program

 

 

 

Status

 

 

 

Operating Mode

 

 

 

Counter (PC)

 

 

Register (SR)

 

 

 

Register (OMR)

 

 

15

0

15

 

 

0

15

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Hardware Stack (HWS)

 

 

 

 

 

 

 

Loop Address (LA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Software Stack

 

12

0

 

 

 

 

 

(Located in X Memory)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Loop Counter (LC)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AA0007

Figure 1-4. DSP56800 Core Programming Model

DSP56824 Overview

1-11

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