Timers

the count register when the timer is enabled, the overflow interrupt occurs after n + 1 input events. After reaching zero, the count register is reloaded with the contents of the preload register. The count register is loaded with a direct value when a direct write to the count register is executed.

The TCT register may also be read or written by a user program. When writing to the TCT register with the corresponding timer disabled, the value is immediately written to the count register and is not overwritten by the value stored in the preload register when the timer is enabled (its TE bit is set). The value stored or written in the preload register is loaded into the count register on the next event after it reaches zero, unless another write to the count register is performed in the meantime. Refer to Section 9.6, “Timer Module Timing Diagrams,” for more details.

NOTE:

The count register can only be written when the corresponding timer is disabled (the TE bit is cleared) in the timer’s control register.

The count register may be read only if one of the following conditions is true:

•The phase lock loop (PLL) is enabled (the PLL enable [PLLE] bit in the PLL Control Register 1 [PCR1] is set) and the prescaler clock is no more than half of the frequency of the Phi clock (that is, the frequency of the prescaler clock is not the same as the frequency of the Phi clock).

•The PLL is bypassed (the PLLE bit in the PCR1 is cleared) and the prescaler within the PLL is set to divide by 1 (the PS[2:0] bits in the PCR1 equal 000).

•The timer with the desired count register is disabled (the TE bit in the appropriate timer’s control register is cleared).

See Section 10.2.1, “PLL Control Register 1 (PCR1),” on page 10-5 for information on the PCR1.

9.2 Timer Resolution

Table 9-6 shows the range of timer interrupt rates (overflow interrupt using the Phi clock) that are provided by the timer count register (TCR2–TCT0) and the timer preload register (TPR2–TCT0).

Table 9-6. Timer Range and Resolution

The value stored in the TPR is the preload count. The overflow interrupt occurs every time the input clock provides a quantity of cycles equal to the preload count + 1.