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Timers

9.1.1.4 Timer Output Enable (TO[1:0])—Bits 11–10, Bits 3–2

The timer output enable (TO[1:0]) control bits (bits 3–2 in TCR01 for Timer 0, bits 11–10 in TCR01 for Timer 1, or bits 3–2 in TCR2 for Timer 2) are used to program the function of the timer output (TIO) pin. Table 9-4 shows the relationship between the value of the TO[1:0] bits and the function of the TIO pin. The TO bits are cleared on reset.

Table 9-4. TIO Pin Function

TO1

TO0

Function of TIO

 

 

 

 

 

Signal on TIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

TIO configured as input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

(Reserved)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

Overflow pulse mode, TIO

 

 

 

 

Icyc/2

 

 

configured as output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

Overflow toggle mode, TIO

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

configured as output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

When the TO[1:0] bits are programmed for overflow pulse mode, the width of the pulse is the period of the internal Phi clock.

NOTE:

For the overflow pulse and overflow toggle modes, it is possible to have more than one timer enabled to drive the TIO pin. In this case, the TIO pin is pulsed or toggled when either counter reaches zero. In this way, it is possible with two timers to generate waveforms on the TIO pin with duty cycles other than 50 percent. Both timers are programmed with the same preload value, but their initial starting value differs. The amount by which their starting values differs determines the duty cycle of the resulting waveform.

It is also acceptable for all timers to be programmed such that no timer drives the TIO pin (TO[1:0] = 00 for the timers). The TIO pin is programmed in this manner when used as input.

NOTE:

If the overflow toggle mode is selected (TO[1:0] = 11) and the TE bit is written as zero while the TIO pin is either high or low, the TIO pin remains in the same state. If the TO1 bit or TO0 bit is written as zero with the TE bit equal to zero, the pin remains high and is driven low when the timer is reenabled.

9.1.1.5 Event Select (ES[1:0])—Bits 9–8, Bits 1–0

The event select (ES[1:0]) control bits (bits 1–0 in TCR01 for Timer 0, bits 9–8 in TCR01 for Timer 1, or bits 1–0 in TCR2 for Timer 2) select the source of the timer clock. If ES[1:0] is 11, an external signal coming from the TIO pin is used as input to the decrement register. The external signal is synchronized to the internal clock as described in Section 9.4, “Event Counting with the Timer Module.” The ES bits are cleared by reset. See Table 9-5 on page 9-7.

9-6

DSP56824 User’s Manual

 

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