DSP56800 Core Description

The RESET pin resets the DSP56824. When it is asserted, it initializes the chip and places it in the Reset state. When the RESET pin is deasserted, the DSP56824 assumes the operating mode indicated by the MODA and MODB pins.

1.2.4 Bit-Manipulation Unit

The Bit Manipulation Unit performs bit-field manipulations on X memory words, peripheral registers, and registers on the DSP56800 core. It is capable of testing, setting, clearing, or inverting any bits specified in a 16-bit mask. For branch-on-bit-field instructions, this unit tests bits on the upper or lower byte of a 16-bit word. In other words, the mask tests a maximum of 8 bits at a time.

Transfers between buses are accomplished in the bus unit. The bus unit is similar to a switch matrix and can connect any two of the three data buses together without adding any pipeline delays. This is required for transferring a core register to a peripheral register, for example, because the core register is connected to the core global data bus (CGDB) bus and the peripheral register is connected to the peripheral global data bus (PGDB).

As a general rule, when reading any register less than 16 bits wide, unused bits are read as zero. Reserved and unused bits should always be written with zero to ensure future compatibility.

1.2.5 Address and Data Buses

Addresses are provided to the internal X data memory on two unidirectional 16-bit buses— X address bus 1 (XAB1) and X address bus 2 (XAB2). Program memory addresses are provided on the unidirectional 16-bit program address bus (PAB). Note that the XAB1 can provide addresses for accessing both internal and external memory, whereas the XAB2 can only provide addresses for accessing internal read-only memory. The external address bus (EAB) provides addresses for external memory.

Data movement on the DSP56824 occurs over three bidirectional 16-bit buses—the core global data bus (CGDB), the program data bus (PDB), and the peripheral global data bus (PGDB)—and also over one unidirectional 16-bit bus, the X data bus 2 (XDB2). Data transfer between the data ALU and the X data memory occurs over the CGDB when one memory access is performed, and over the CGDB and the XDB2 when two simultaneous memory reads are performed. All other data transfers to core blocks occur over the CGDB, and all transfers to and from peripherals occur over the PGDB. Instruction word fetches occur simultaneously over the PDB. The external data bus (EDB) provides bidirectional access to external data memory.

The bus structure supports general register-to-register, register-to-memory, and memory-to-register transfers, and can transfer up to three 16-bit words in the same instruction cycle. Transfers between buses are accomplished in the bit-manipulation unit. Table 1-1 lists the address and data buses for the DSP56800 core.

Table 1-1. DSP56800 Address and Data Buses