Synchronous Serial Interface

8.4.2 Network Mode

Network mode is used for creating a time division multiplexed (TDM) network, such as a TDM codec network or a network of DSPs. In continuous clock mode, a frame sync occurs at the beginning of each frame. In this mode, the frame is divided into more than one time slot. During each time slot, one data word can be transferred. Each time slot is then assigned to an appropriate codec or DSP on the network. The DSP can be a master device that controls its own private network, or a slave device that is connected to an existing TDM network and occupies a few time slots.

The frame sync signal indicates the beginning of a new data frame. Each data frame is divided into time slots, and transmission or reception (or both) of one data word can occur in each time slot (rather than in just the frame sync time slot as in normal mode). The frame rate dividers, controlled by the DC[4:0] bits, select 2 to 32 time slots per frame. The length of the frame is determined by the following factors:

•The period of the serial bit clock (PSR, PM[7:0] bits for internal clock, or the frequency of the external clock on the STCK pin)

•The number of bits per sample (WL[1:0] bits)

•The number of time slots per frame (DC[4:0] bits)

In network mode, data can be transmitted in any time slot. The distinction of the network mode is that each time slot is identified with respect to the frame sync (data word time). This time slot identification allows the option of transmitting data during the time slot by writing to the STX register or ignoring the time slot by writing to STSR. The receiver is treated in the same manner, except that data is always being shifted into the RXSR and transferred to the SRX register. The DSP56824 reads the SRX register and either uses it or discards it.

8.4.2.1 Network Mode Transmit

The transmit portion of SSI is enabled when the SSIEN and the TE bits in the SCR2 are both set. However, for continuous clock, when the TE bit is set, the transmitter is enabled only after detection of a new time slot (if the TE bit is set during a slot other than the first). Software has to find the start of the next frame.

The normal startup sequence for transmission is to do the following:

1.Write the data to be transmitted to the STX register. This clears the TDE flag.

2.Set the TE bit to enable the transmitter on the next word boundary (for a continuous clock case).

3.Enable transmit interrupts.

Alternatively, the programmer may decide not to transmit in a time slot by writing to the STSR. This clears the TDE flag just as if data were going to be transmitted, but the STD pin remains tri-stated during the time slot.

When the frame sync is detected or generated (continuous clock), the first enabled data word is transferred from the STX register to the TXSR and is shifted out (transmitted). When the STX register is empty, the TDE bit is set, which causes a transmitter interrupt to be sent if the TIE bit is set. Software can poll the TDE bit or use interrupts to reload the STX register with new data for the next time slot or write to the STSR to prevent transmitting in the next time slot. Failing to reload the STX register (or writing to the STSR) before the TXSR is finished shifting (empty) causes a transmitter underrun and the TUE error bit to be set, and the STD pin is tri-stated for the next time slot.

The operation of clearing the TE bit disables the transmitter after the completion of the transmission of the current data word. Setting the TE bit enables the transmission of the next word. During that time the STD pin is tri-stated. The TE bit should be cleared after the TDE bit is set to ensure that all pending data is transmitted.