Synchronous Serial Interface

8.4.1 Normal Mode

Normal mode is the simplest mode of the SSI. It is used to transfer one word per frame. In continuous clock mode, a frame sync occurs at the beginning of each frame.

The length of the frame is determined by the following factors:

•The period of the serial bit clock (PSR, PM[7:0] bits for internal clock or the frequency of the external clock on the STCK pin)

•The number of bits per sample (WL[1:0] bits)

•The number of time slots per frame (DC[4:0] bits)

If normal mode is configured to provide more than one time slot per frame, data is transmitted only in the first time slot. No data is transmitted in subsequent time slots.

8.4.1.1 Normal Mode Transmit

The conditions for data transmission from the SSI in normal mode are:

1.SSI enabled (SSIEN = 1)

2.Transmitter enabled (TE = 1)

3.Frame sync active (for continuous clock case)

4.Bit clock begins (for gated clock case)

When the preceding conditions occur in normal mode, the next data word is transferred into the TXSR from the STX register, or from the transmit data buffer register, if transmit buffering is enabled. The new data word is transmitted immediately. If buffering is not enabled, the TDE bit is set (transmitter empty), and the transmit interrupt occurs if the TIE bit is set (transmit interrupt is enabled). If buffering is enabled, the TDE bit is set (transmitter empty) and the transmit interrupt occurs, if the TIE bit is set (transmit interrupt is enabled), when both values have been transferred to the TXSR. If buffering is enabled, a second data word can be transferred and shifted before the DSP56824 must write new data to the STX register.

The STD pin is tri-stated except during the data transmission period. For a continuous clock, the optional frame sync output and clock outputs are not tri-stated, even if both receiver and transmitter are disabled.

8.4.1.2Normal Mode Receive

The conditions for data reception from the SSI are:

1.SSI enabled (SSIEN = 1)

2.Receiver enabled (RE = 1)

3.Frame sync active (for continuous clock case)

4.Bit clock begins (for gated clock case)

With the preceding conditions in normal mode with a continuous clock, each time the frame sync signal is generated (or detected), a data word is clocked in. With the preceding conditions and a gated clock, each time the clock begins, a data word is clocked in. If buffering is not enabled, the data word, after being received, is transferred from the RXSR to the SRX register, the RDF flag is set (receiver full), and the receive interrupt occurs if it is enabled (the RIE bit is set). If buffering is enabled, the data word, after being received, is transferred to the receive data buffer register. The RDF flag is set if both the SRX register and receive data buffer register are full, and the receive interrupt occurs if it is enabled (the RIE bit is set).

SSI Operating Modes

The DSP56824 program has to read the data from the SRX register before a new data word is transferred from the RXSR; otherwise the ROE bit is set. If buffering is enabled, the ROE bit is set when both the SRX register and the receive data buffer register contain data and a new data word is ready to be transferred to the receive data buffer register.

Figure 8-12 shows transmitter and receiver timing for an 8-bit word with two words per time slot in normal mode, continuous clock, with a late word length frame sync.

Continuous

CLK

FS

TX

Data

STD

SRD

RX

Data

AA0161

Figure 8-12. Normal Mode Timing—Continuous Clock

Figure 8-13 shows a similar case for gated clock. Note that a pull-down resistor is required in the gated clock case because the clock pin is tri-stated between transmissions.

Gated

CLK

TX

Data

STD

SRD

RX

Data

AA1440

Figure 8-13. Normal Mode Timing—Gated Clock