SSI Programming Model

8.2.8.3 Receive Enable (RE)—Bit 13

The SSI receive enable (RE) control bit enables the receive portion of the SSI. When the RE bit is set, the receive portion of the SSI is enabled. When the RE bit is cleared, the receiver is disabled by inhibiting data transfer into the receive (RX) buffer. If data is being received when this bit is cleared, the rest of the word is not shifted in, nor is it transferred to the SRX register. If the RE bit is reenabled during a time slot before the second-to-last bit, then the word will be received.

8.2.8.4 Transmit Enable (TE)—Bit 12

The SSI transmit enable (TE) control bit enables the transfer of the contents of the STX register to the transmit shift register and also enables the internal gated clock. When the TE bit is set and a word boundary is detected, the transmit portion of the SSI is enabled. When the TE bit is cleared, the transmitter continues to send the data currently in the SSI transmit shift register and then disables the transmitter. The serial output is tri-stated and any data present in the STX register is not transmitted. In other words, data can be written to the STX register with the TE bit cleared, and the TDE bit is cleared but data is not transferred to the transmit shift register. If the TE bit is cleared and then set again during the same transmitted word, the data continues to be transmitted. If the TE bit is set again during a different time slot, data is not transmitted until the next word boundary.

The normal transmit-enable sequence is to write data to the STX register or to the STSR before setting the TE bit. The normal transmit-disable sequence is to clear the TE bit and the TIE bit after the TDE bit is set. When an internal gated clock is being used, the gated clock runs during valid time slots if the TE bit is set. If the TE bit is cleared, the transmitter continues to send the data currently in the SSI transmit shift register until it is empty. Then the clock stops. When the TE bit is set again, the gated clock starts immediately and runs during any valid time slots.

8.2.8.5 Receive Buffer Enable (RBF)—Bit 11

The receive buffer enable (RBF) control bit enables the buffer register for the receive section. When the RBF bit is set, it allows for two samples to be received by the SSI (a third sample can be shifting in) before the RDF bit is set and for an interrupt request to be generated when enabled by the RIE bit. When the RBF bit is cleared, the buffer register is not used, and an interrupt request is generated when a single sample is received by the SSI. (Interrupts need to be enabled.)

8.2.8.6 Transmit Buffer Enable (TBF)—Bit 10

The transmit buffer enable (TBF) control bit enables the buffer register for the transmit section. When the TBF bit is set, two samples can be written to the SSI (a third sample can be shifting out) before the TDE bit is set, and an interrupt request can be generated when enabled by the TIE bit. When the TBF bit is cleared, the buffer register is not used, and an interrupt request is generated when a single sample needs to be written to the SSI.

8.2.8.7 Receive Direction (RXD)—Bit 9

The receive direction (RXD) control bit selects the direction and source of the clock and frame sync signals used to clock the RXSR. When the RXD bit is set, the frame sync and clock are generated internally and are output to the SRFS and SRCK pins, respectively, if not configured as general-purpose input/output (GPIO). When the RXD bit is cleared, the clock source is external, the internal clock generator is disconnected from the SRCK pin, and an external clock source can drive this pin to clock the RXSR. The SRFS pin is an input, meaning that the receive frame sync is supplied from an external source. Table 8-5 shows the frame sync and clock pin configuration.