DSP56800 Core Description

The On-Chip Emulation (OnCE) module allows the user to interact in a debug environment with the DSP56800 core and its peripherals non-intrusively. Its capabilities include examining registers, memory, or on-chip peripherals; setting breakpoints in memory; and stepping or tracing instructions. It provides simple, inexpensive, and speed-independent access to the DSP56800 core for sophisticated debugging and economical system development. The JTAG/OnCE port allows access to the OnCE module and through the DSP56824 to its target system, retaining debug control without sacrificing other user-accessible on-chip resources.

1.1.2 DSP56824 Peripheral Interrupts

The peripherals on the DSP56824 use the interrupt channels found on the DSP56800 core. Each peripheral has its own interrupt vector (often more than one interrupt vector for each peripheral) and can selectively be enabled or disabled via the interrupt priority level found on the DSP56800 core.

Chapter 3, “Memory Configuration and Operating Modes,” provides complete details on interrupt vectors.

1.2 DSP56800 Core Description

The DSP56800 core consists of functional units that operate in parallel to increase the throughput of the machine. Major features of the DSP56800 core include the following:

•Single-cycle 16-bit x 16-bit parallel multiply-accumulator (MAC)

•Two 36-bit accumulators including extension bits

•16-bit bidirectional barrel shifter

•Highly parallel instruction set with unique DSP and controller addressing modes

•Nested hardware DO loops

•Software subroutine and interrupt stack with unlimited depth

•Instruction set that supports both DSP and controller functions for compact code

•Efficient C Compiler and local variable support

An overall block diagram of the DSP56800 core architecture is shown in Figure 1-2 on page 1-6. The DSP56800 core is fed by internal program and data memory, an external memory interface, and various peripherals suitable for embedded applications. The blocks of the DSP56800 core include the following:

•Data arithmetic logic unit (Data ALU)

•Address generation unit (AGU)

•Program controller and hardware looping unit

•Bit-manipulation unit

•Address buses

•Data buses

DSP56824 Overview

Figure 1-2. DSP56800 Core Block Diagram

The program controller, AGU, and data ALU each contain a discrete register set and control logic, so that each can operate independently and in parallel with the others. Likewise, each functional unit interfaces with other units, with memory, and with memory-mapped peripherals over the core’s internal address and data buses, as shown in Figure 1-3 on page 1-7.

DSP56800 Core Description

Figure 1-3. DSP56800 Bus Block Diagram

It is possible in a single instruction cycle for the program controller to be fetching a first instruction, the AGU to generate two addresses for a second instruction, and the data ALU to perform a multiply in a third instruction. In a similar manner, the bit manipulation unit can perform an operation of the third instruction described above instead of the multiplication in the data ALU. The architecture is pipelined to take advantage of the parallel units and significantly decrease the execution time of each instruction.

1.2.1 Data Arithmetic Logic Unit (Data ALU)

The data arithmetic logic unit (data ALU) performs all of the arithmetic and logical operations on data operands. It contains the following:

•Three 16-bit input registers

•Two 32-bit accumulator registers

•Two 4-bit accumulator extension registers

•One parallel, single cycle, non-pipelined MAC unit

•An accumulator shifter

DSP56824 Overview

•One data limiter

•One MAC output limiter

•One 16-bit barrel shifter

The data ALU is capable of performing the following in one instruction cycle:

•Multiplication

•Multiply-accumulation with positive or negative accumulation

•Addition

•Subtraction

•Shifting

•Logical operations

Arithmetic operations are done using two’s-complement fractional or integer arithmetic. Support is also provided for unsigned and multi-precision arithmetic.

Data ALU source operands can be 16, 32, or 36 bits and can originate from input registers or accumulators. ALU results are stored in one of the accumulators. In addition, some arithmetic instructions store their 16-bit results in any of the three data ALU input registers or write directly to memory. Arithmetic operations and shifts have a 16-bit or 36-bit result, and logical operations are performed on 16-bit operands yielding 16-bit results. Data ALU registers can be read or written by the core global data bus (CGDB) as 16-bit operands, and the X0 register can also be written by the X data bus 2 (XDB2) with a 16-bit operand.

1.2.2 Address Generation Unit (AGU)

The address generation unit (AGU) performs all of the effective address calculations and address storage necessary to address data operands in memory. This unit operates in parallel with other chip resources to minimize address-generation overhead. It contains two ALUs, allowing the generation of up to two 16-bit addresses every instruction cycle—one for either the XAB1 or PAB bus and one for the XAB2 bus. The ALU can directly address 65,536 locations on the XAB1 or XAB2 bus and 65,536 locations on the program address bus (PAB), for a total capability of 131,072 words of 16-bit data. Hooks are provided on the DSP56800 core to expand this address space. Its arithmetic unit can perform linear and modulo arithmetic.

1.2.3 Program Controller and Hardware Looping Unit

The program controller performs instruction prefetching, instruction decoding, hardware loop control, and interrupt (exception) processing. Instruction execution is carried out in other core units, such as the data ALU or AGU. The program controller consists of a program counter (PC) unit, hardware looping control logic, interrupt control logic, and status and control registers.

Two mode and interrupt control pins provide input to the program interrupt controller. The Mode Select A/External Interrupt Request A (MODA/IRQA) pin and the

Mode Select B/External Interrupt Request B (MODB/IRQB) pin select the DSP56824 operating mode and receive interrupt requests from external sources.