Synchronous Serial Interface

8.2 SSI Programming Model

The registers associated with the SSI include the following:

•SSI transmit shift register (TXSR, not user accessible)

•SSI transmit data buffer register (not user accessible)

•SSI transmit data (STX, write-only) register

•SSI receive shift register (RXSR, not user accessible)

•SSI receive data buffer register (not user accessible)

•SSI receive data (SRX, read-only) register

•SSI transmit control register (SCRTX)

•SSI receive control register (SCRRX)

•SSI control register 2 (SCR2)

•SSI control/status register (SCSR, lower byte read-only)

•SSI time slot register (STSR, write-only)

The control registers associated with the SSI are shown in Figure 8-6 on page 8-7; Figure 8-7 on page 8-10 shows the programming information for SSI interrupts. Table 3-6, “Interrupt Priority Structure,” on

page 3-16 lists the interrupt priority order for the DSP56824.

The TXSR, RXSR, receive data buffer register, and transmit data buffer register are not user accessible.

NOTE:

To use the SSI, the CC[13:8] bits in the Port C control (PCC) register must be correctly set. See Section 8.6, “Configuring Port C for SSI Functionality,” for more information.

SSI Programming Model

STSR— X:$FFD5

SSI Time Slot Register Dummy Register, Written During Inactive Time Slots (Network Mode) Write-Only

Synchronous Serial Interface

Figure 8-7. SSI Interrupt Vectors

8.2.1 SSI Transmit Shift Register (TXSR)

The SSI transmit shift register (TXSR) is a 16-bit shift register that contains the data being transmitted. When a continuous clock is used, data is shifted out to the serial transmit data (STD) pin by the selected (internal/external) bit clock when the associated (internal/external) frame sync is asserted. When a gated clock is used, data is shifted out to the STD pin by the selected (internal/external) gated clock. The word length control bits (WL[1:0]) in the SCRTX, described in Section 8.2.7, “SSI Transmit and Receive Control Registers,” determine the number of bits to be shifted out of the TXSR before it is considered empty and can be written to again. This word length can be 8, 10, 12, or 16 bits. The data to be transmitted occupies the most significant portion of the shift register. The unused portion of the register is ignored. Data is always shifted out of this register with the most significant bit (MSB) first when the SHFD bit of the SCR2 is cleared. If this bit is set, the least significant bit (LSB) is shifted out first.

8.2.2 SSI Transmit Data Buffer Register

The SSI transmit data buffer register is a 16-bit register used to buffer samples written to the STX register. It is written by the contents of the STX register whenever the transmit buffer feature is enabled. When it is enabled, the TXSR receives its values from this buffer register. If the transmit buffer feature is not enabled, this register is bypassed and the contents of the STX register is transferred into the TXSR.

When the transmit interrupt enable (TIE) bit in the SCR2 and TDE bit in the SCSR are set, the DSP56824 is interrupted whenever both the STX register and the SSI transmit data buffer register become empty.

8.2.3 SSI Transmit Data (STX) Register

The SSI transmit data (STX) register is a 16-bit, write-only register. Data to be transmitted is written into this register. If the transmit buffer is used, data is transferred from this register to the transmit data buffer register when it becomes empty. Otherwise, data written to this register is transferred to the TXSR when shifting of previous data is completed. The data written occupies the most significant portion of the STX register. The unused bits (least significant portion) of the STX register are ignored. The DSP56824 is interrupted whenever the STX register becomes empty (when both the STX register and SSI transmit data buffer register are empty, if buffering is enabled) if both the transmit data register empty (TDE) bit in the SCSR and the TIE bit in the SCR2 are set.