Synchronous Serial Interface

8.1.1 SSI Clocking

The SSI uses the following three clocks:

•Bit clock—used to serially clock the data bits in and out of the SSI port

•Word clock—used to count the number of data bits per word (8, 10, 12, or 16 bits)

•Frame clock—used to count the number of words in a frame

The bit clock, used to serially clock the data, is visible on the serial transmit clock (STCK) and serial receive clock (SRCK) pins. The word clock is an internal clock used to determine when transmission of an 8-, 10-, 12-, or 16-bit word has completed. The word clock in turn then clocks the frame clock, which counts the number of words in the frame. The frame clock can be viewed on the STFS and SRFS frame sync pins, because a frame sync is generated after the correct number of words in the frame have passed. The relationship between the clocks and the dividers is shown in Figure 8-3 on page 8-4. The bit clock can be received from an SSI clock pin or can be generated from the Phi clock through a divider, as shown in Figure 8-4 on page 8-5.

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Figure 8-3. SSI Clocking

8.1.2 SSI Clock and Frame Sync Generation

Data clock and frame sync signals can be generated internally by the DSP56824 or can be obtained from external sources. If the signals are internally generated, the SSI clock generator is used to derive bit clock and frame sync signals from the Phi clock. The SSI clock generator consists of a selectable, fixed prescaler and a programmable prescaler for bit-rate clock generation. In gated clock mode, the data clock is valid only when data is being transmitted. Otherwise the clock pin is tri-stated. A programmable frame rate divider and a word length divider are used for frame rate sync signal generation.

Figure 8-4 shows a block diagram of the clock generator for the transmit section. The serial bit clock can be internal or external, depending on the transmit direction (TXD) bit in the SSI control register 2 (SCR2) control register. The receive section contains an equivalent clock generator circuit.

SSI Architecture

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Figure 8-4. SSI Transmit Clock Generator Block Diagram

Figure 8-5 on page 8-5 shows the frame sync generator block for the transmit section. When internally generated, both receive and transmit frame sync are generated from the word clock and are defined by the frame rate divider (DC[4:0]) bits and the word length (WL[1:0]) bits of the SSI transmit control register (SCRTX). The receive section contains an equivalent circuit for the frame sync generator.

FSI

TX Frame

TX Sync In

Control

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Figure 8-5. SSI Transmit Frame Sync Generator Block Diagram