Configuring Port C for SPI Functionality
7.5 Configuring Port C for SPI Functionality
The PCC register is used to individually configure each pin as either an SPI pin or a GPIO pin. When the SPI is used in Slave mode, all four SPI pins must be programmed as SPI pins in the PCC register. When in Master mode, the SCK, MISO, and MOSI pins are configured as SPI pins, and the SS pin is optionally configured as an SPI pin if mode-fault detection is desired. Otherwise, SS can be configured as a GPIO pin in the PCC register. This is summarized in Table 7-4.
Table 7-4. PCC Register Programming for the SS Pin
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CC Bit1 |
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Mode |
Functionality of the SS Pin |
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Slave |
0 |
Not allowed |
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Slave |
1 |
Used as |
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pin |
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SS |
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Master |
0 |
Used as GPIO pin |
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Master |
1 |
Used for mode-fault detection |
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1.For SPI0, use PCC[3]. For SPI1, use PCC[7].
When the PCC register bit is set for an SPI pin, it is not necessary to program the corresponding PCDDR bit. The SPI peripheral ensures the correct direction of this pin. Programming the PCDDR is necessary only when a pin is programmed as a GPIO pin.
In applications requiring minimum power consumption, the SPI module can be disabled by clearing the SPE bit in SPCR. This also shuts off the Phi clock signal as it enters the block.
Stop mode automatically disables the SPI peripheral and any external clocks for devices configured in Slave mode. The internal Phi clock is stopped in stop mode. If a device is in the middle of a transfer when it enters stop mode, all internal state machines are reset so that, upon exiting stop mode, the device waits for a new transfer to be initiated.
In wait mode, the SPI peripheral continues operation and can complete transfers in progress. If the SPI interrupt is enabled in the SPCR, IPR, and SR, the SPI peripheral can generate an interrupt request in wait mode that brings the DSP56824 out of wait mode.
7.6 Programming Examples
Example 7-1 through Example 7-3 on page 7-17 show how to configure one SPI port as a master, how to configure one as a slave, and how to send data from master to slave.
7.6.1 Configuring an SPI Port as Master
Example 7-1 shows how to configure an SPI port as a master.
Serial Peripheral Interface |
7-13 |
Serial Peripheral Interface
Example 7-1. Configuring an SPI Port as Master
;******************************************
;* SPI master |
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* |
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;* for serial peripheral interface (SPI)* |
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;* of DSP56824 chip |
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* |
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;****************************************** |
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START |
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EQU |
$0040 |
; Start of program |
BCR |
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EQU |
$FFF9 |
; Bus Control Register |
IPR |
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EQU |
$FFFB |
; Interrupt Priority Register |
PCC |
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EQU |
$FFED |
; Port C Control Register |
PCDDR |
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EQU |
$FFEE |
; Port C Data Direction Register |
PCR0 |
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EQU |
$FFF2 |
; PLL Control Register 0 |
PCR1 |
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EQU |
$FFF3 |
; PLL Control Register 1 |
SPCR0 |
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EQU |
$FFE2 |
; SPI0 Control Register |
SPDR0 |
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EQU |
$FFE0 |
; SPI0 Data Register |
SPSR0 |
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EQU |
$FFE1 |
; SPI0 Status Register |
;************** |
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;* Vector setup* |
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;************** |
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ORG |
P:$0000 |
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; Cold Boot |
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JMP |
START |
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; also Hardware RESET vector (Mode 0, 1, 3) |
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ORG |
P:$E000 |
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; Warm Boot |
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JMP |
START |
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; Hardware RESET vector (Mode 2) |
; |
ORG |
P:$0028 |
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; |
; |
JSR |
[unused] |
; SPI1 Serial System vector |
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ORG |
P:START |
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; Start of program |
;***************** ;* General setup * ;***************** MOVEP
7-14 |
DSP56824 User’s Manual |
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Programming Examples
Example 7-1. Configuring an SPI Port as Master (Continued)
;********************************************************* ;* Phi Clock included for serial bit clock of SPI Master * ;*********************************************************
MOVEP |
#$0180,X:PCR1 |
;Configure: |
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;(PLLE) PLL disabled (bypassed) |
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; -- Oscillator supplies Phi clock. |
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;(PLLD) PLL Power Down disabled (PLL active). |
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; -- PLL block active for PLL to attain lock. |
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;(LPST) Low Power Stop disabled. |
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;(PS[2:0]) Prescaler Clock disabled. |
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;(CS[1:0]) Clockout pin sends Phi clock. |
MOVEP |
#$0260,X:PCR0 |
; Set Feedback Divider to 1/20 |
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; ... |
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; insert delay here: wait for PLL lock |
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; as specified in data sheet |
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; ... |
BFSET |
#$4000,X:PCR1 |
; Enable PLL for Phi clock. |
;******************** |
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;* SPI Master setup * |
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;******************** |
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BFCLR |
#$0040,X:SPCR0 |
; (SPE) SPI disabled |
MOVEP |
#$0116,X:SPCR0 |
; Configure: |
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; (SPR[2:0]) SPI Clock Rate Select at /64. |
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; (SPIE) SPI Interrupt disabled. |
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; (WOM) Wired-OR mode disabled: |
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; - push-pull drivers. |
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; (MST) Master mode selected. |
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; (CPL) serial Clock Polarity: |
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; - SCK pin idles as logic low. |
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; (CPH) Clock Phase protocol: |
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; - ~SS line can be tied low if only 1 slave. |
BFSET |
#$0007,X:PCC |
; Configure: |
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; MISO0, MOSI0, SCK0 for SPI master, |
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; ~SS0 as PC3 for GPIO. |
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; Other pins remain as previously set. |
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; (reset default is GPIO). |
BFSET |
#$0008,X:PCDDR |
; Configure GPIO pin PC3 as output |
BFCLR |
#$2000,X:IPR |
; Disable SPI0 interrupts |
completeness). |
; (unnecessary but mentioned for |
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BFSET |
#$0040,X:SPCR0 |
; (SPE) SPI Enabled. |
;**************** |
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;* Main routine * |
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;**************** |
; ... |
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TEST |
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; Test Loop |
BRA |
TEST |
; ... |
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Serial Peripheral Interface |
7-15 |