SPI Data and Control Pins

7.2.2.3 Write Collision (WCOL)—Bit 6

The write collision (WCOL) flag bit is set when a write collision condition is detected. This bit is cleared by reading the SPSR (with MDF set) followed by an access of the SPDR. The WCOL flag is cleared on hardware reset.

7.2.2.4 Reserved Bit—Bit 5

Bit 5 of SPSR0 and SPSR1 is reserved and is read as zero during read operations. This bit should be written with zero to ensure future compatibility.

7.2.2.5 Mode Fault (MDF)—Bit 4

The mode fault (MDF) flag is set when a mode fault has occurred. This bit is cleared by reading the SPSR (with MDF set) followed by a write to the SPCR. The MDF flag is cleared on hardware reset.

7.2.2.6 Reserved Bits—Bits 3–0

Bits 3–0 of SPSR0 and SPSR1 are reserved and are read as zero during read operations. These bits should be written with zero to ensure future compatibility.

7.2.3 SPI Data Registers (SPDR0 and SPDR1)

The SPI data registers (SPDR0 and SPDR1) are 16-bit read/write registers used when the SPI devices are transmitting or receiving data on the serial bus. Only a write to one of these registers initiates the transmission or reception of a byte, and this only occurs on the master device. At the completion of transferring a byte of data, the SPIF status bit (in the corresponding SPSR) is set in both the master and slave devices.

A read of an SPDR is actually a read of a buffer. To prevent an overrun and the loss of the byte that caused the overrun, the first SPIF must be cleared by the time a second transfer of data from the shift register to the read buffer is initiated. This register is double-buffered for input and single-buffered for output.

7.3 SPI Data and Control Pins

During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). An SCK line synchronizes shifting and sampling of the information on the two serial data lines. An SS line allows individual selection of a slave SPI device. Slave devices that are not selected do not interfere with SPI bus activities. On a master SPI device, the select line can optionally be used to indicate a multiple-master bus contention.

Each SPI device has four dedicated I/O pins. The four pins on SPI0 are as follows:

•MISO0/PC0 (SPI0 master in/slave out)—The MISO0 pin carries one of two unidirectional serial data signals. It is an input to a master device and an output from a slave device. If a slave device is not selected, the MISO0 line of the slave device is placed in the high-impedance state. MISO0 can be programmed as a GPIO pin called PC0 when the SPI MISO0 function is not being used.

Serial Peripheral Interface

•MOSI0/PC1 (SPI0 master out/slave in)—The MOSI0 pin carries the second of the two unidirectional serial data signals. It is an output from a master device and an input to a slave device. The master device places data on the MOSI0 line a half-cycle before the clock edge that the slave device uses to latch the data. MOSI0 can be programmed as a general-purpose input/output (GPIO) pin called PC1 when the SPI MOSI0 function is not being used.

•SCK0/PC2 (SPI0 serial clock)—SCK0, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the MOSI0 and MISO0 lines. Master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Slave devices ignore the SCK signal unless the slave select pin is active low.

Four possible timing relationships can be chosen by using the CPL and CPH control bits in the SPCR. Both master and slave devices must operate with the same timing. The SPI clock rate select bits, SPR[2:0], in the SPCR of the master device, select the clock rate. In a slave device, the SPR[2:0] bits have no effect on the operation of the SPI. The SCK0 pin can be programmed as a GPIO pin (PC2) when the SPI SCK0 function is not being used.

•SS0/PC3 (SPI0 slave select)—The slave select (SS) input of a slave device must be externally asserted before a master device can exchange data with the slave device. SS must be low before data transactions and must stay low for the duration of the transaction. The SS line of the master must be held high. If it goes low, a mode fault error flag (the MDF bit) is set in the SPSR. To disable the mode fault circuit, program the SS pin as a GPIO pin in the PCC register. This inhibits the mode fault flag, while the other three lines are dedicated to the SPI peripheral.

The state of the master and slave CPH bits (in the SPCR) affects the operation of SS. The CPH bit settings should be the same for both master and slave. When the CPH bit is cleared, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high between successive bytes in an SPI message. When the CPH bit is set, SS can be left low between successive SPI bytes. In cases where there is only one SPI slave MCU, its SS line can be tied to VSS as long as only CPH = 1 clock mode is used. The SS0 pin can be programmed as a GPIO pin (PC3) when the SPI SS0 function is not being used.

The four pins on SPI1 are as follows:

•MISO1/PC4 (SPI1 master in/slave out)—MISO1 is one of two unidirectional serial data signals. It is an input to a master device and an output from a slave device. If a slave device is not selected, the MISO0 line of the slave device is placed in the high-impedance state. MISO1 can be programmed as a GPIO pin called PC4 when the SPI MISO1 function is not being used.

•MOSI1/PC5 (SPI1 master out/slave in)—The MOSI1 line is the second of the two unidirectional serial data signals. It is an output from a master device and an input to a slave device. The master device places data on the MOSI1 line a half-cycle before the clock edge that the slave device uses to latch the data. MOSI1 can be programmed as a GPIO pin called PC5 when the SPI MOSI1 function is not being used.

•SCK1/PC6 (SPI1 serial clock)—SCK1, an input to a slave device, is generated by the master device and synchronizes data movement in and out of the device through the MOSI1 and MISO1 lines. Master and slave devices are capable of exchanging a byte of information during a sequence of eight clock cycles. Slave devices ignore the SCK signal unless the SS pin is active low.

Four possible timing relationships can be chosen by using the CPL and CPH control bits in the SPCR. Both master and slave devices must operate with the same timing. The SPI clock rate select bits (SPR[2:0]), in the SPCR of the master device, select the clock rate. In a slave device, the SPR[2:0] bits have no effect on the operation of the SPI. The SCK1 pin can be programmed as a GPIO pin (PC6) when the SPI SCK1 function is not being used.