DSP56824 Architecture Overview

1.1.1 DSP56824 Peripheral Blocks

The DSP56824 provides the following peripheral blocks:

•On-chip memory

—32K × 16 program ROM

—128 × 16 program RAM

—3.5K × 16 RAM for data and applications

—2K × 16 data ROM

•External memory interface

•GPIO module

•Programmable I/O module

•Serial peripheral interface (SPI—two provided)

•Synchronous serial interface (SSI)

•General-purpose triple timer module

•On-chip clock synthesis block (phase lock loop or PLL)

•Computer Operating Properly (COP) and real-time interrupt (RTI) module

•JTAG/OnCE™ Port

1.1.1.1 On-Chip Memory

The DSP56824 uses a Harvard architecture, which provides independent data and program memory. On-chip ROM is provided for both the X data (2K × 16-bit) and program (P) memory (32K × 16-bit). In addition, on-chip RAM is provided for both the X data (3.5K × 16-bit) and P memory (128 × 16-bit). Both the program and data memories can be expanded off-chip.

1.1.1.2 External Memory Interface (Port A)

The DSP56824 provides an external memory interface, also known as Port A. This port provides a total of 36 pins—16 pins for an external address bus, 16 pins for an external data bus, and 4 pins for bus control.

1.1.1.3 General-Purpose Input/Output Port (Port B)

A dedicated general-purpose input/output (GPIO) port, also known as Port B, provides 16 programmable I/O pins. This port is configured so that it is possible to generate interrupts when a transition is detected on any of its lower eight pins.

1.1.1.4 Programmable I/O Port (Port C)

Port C provides 16 multiplexed general-purpose programmable I/O pins. Each pin can be individually selected as a GPIO pin or allocated to on-chip peripherals—the general-purpose timer module, two SPIs, and an SSI. Unlike the GPIO pins on Port B, the Port C pins cannot be configured to provide GPIO interrupts, but interrupts are available for the timer module, the two SPI ports, and the SSI port on Port C.

DSP56824 Overview

1.1.1.5 Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) is an independent serial communications subsystem that allows the DSP56824 to communicate synchronously with peripheral devices such as LCD display drivers, A/D subsystems, and MCU microprocessors. The SPI is also capable of interprocessor communication in a multiple master system. The SPI system can be configured as either a master or a slave device with high data rates. The SPI works in a demand-driven mode. In Master mode, a transfer is initiated when data is written to the SPI Data Register. In Slave mode, a transfer is initiated by the reception of a clock signal. Two separate SPIs are implemented on Port C.

1.1.1.6 Synchronous Serial Interface (SSI)

The synchronous serial interface (SSI) is a full-duplex serial port that allows the DSP56824 to communicate with a variety of multiple serial devices including industry-standard codecs, other DSPs, microprocessors, and peripherals that implement the Motorola SPI. It is typically used to transfer samples in a periodic manner. The SSI consists of independent transmitter and receiver sections with independent clock generation and frame synchronization. The SSI is implemented on Port C.

1.1.1.7 General-Purpose Timer Module

The timer module provides three independently programmable 16-bit timer/event counters. All three timer/counters can be clocked with clocks coming from one of three internal sources, including one of the other timers. In addition, the counters can be clocked with external clocking from the timer I/O pins (TIO01 or TIO2) on Port C to count external events when configured as inputs. The same pins can be used as a timer pulse or for timer clock generation when used as outputs. The timer/event counters can be used to either interrupt the DSP56824 or to signal an external device at periodic intervals. The timer I/O pins are implemented as part of Port C.

1.1.1.8 On-Chip Clock Synthesis Block

The clock synthesis module generates the clocking for the DSP56824. It generates three different clocks used by the DSP56800 core and DSP56824 peripherals. It contains a PLL that can multiply up the frequency or can be bypassed, and also contains a prescaler/divider used to distribute clocks to peripherals and to lower power consumption on the DSP56824. It also selects which clock, if any, is routed to the CLKO pin of the DSP56824.

1.1.1.9 COP/RTI Module

The Computer Operating Properly (COP) and real-time interrupt (RTI) module provides two separate functions: a watchdog timer and an interrupt generator. These two functions monitor processor activity and provide an automatic reset signal if a failure occurs. Both functions are contained in the same block because the input clock for both comes from a common clock divider.

1.1.1.10 JTAG/OnCE™ Port

The JTAG/OnCE port allows the user to insert the DSP56824 into a target system while retaining debug control. The JTAG port provides board-level testing capability that is compatible with the IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1a-1993) specification defined by the Joint Test Action Group (JTAG). Five dedicated pins interface to a test access port (TAP) that contains a 16-state controller.