Serial Peripheral Interface

7.2.1 SPI Control Registers (SPCR0 and SPCR1)

The SPI control registers (SPCR0 and SPCR1) are 16-bit, read/write registers used to set up and control the SPI0 and SPI1 peripherals, respectively. The bits within the registers are arranged and programmed identically. The only differences are that the two registers have different addresses and control different SPIs. Programming one register has no effect on the other register.

The WOM, MST, CPL, CPH, and the SPR[2:0] bits should not be changed when a transfer is taking place. Typically, these bits are only modified in Slave mode when the SPE bit is cleared, when the device is not selected, or in Master mode when no transfer is in progress.

NOTE:

When writing the SPCR0 or the SPCR1, it is necessary to first write the register with the SPE bit cleared. Then a second write is performed to the SPCR with the same value except that the SPE bit is set. The BFSET instruction can be used in place of this second write to set the SPE bit. This is true for all bits in the SPCR except the SPIE bit, which can be modified with a BFSET or BFCLR instruction at any time, even when the SPE bit is set.

The SPCR0 and SPCR1 are reset to $0000 on hardware reset. The bits of the SPCR0 and SPCR1 are described in Section 7.2.1.1, “Reserved Bits—Bits 15–9,” through Section 7.2.1.8, “Clock Phase (CPH)—Bit 2.”

7.2.1.1 Reserved Bits—Bits 15–9

Bits 15–9 of the SPCR0 and SPCR1 are reserved and are read as zero during read operations. These bits should be written with zero to ensure future compatibility.

7.2.1.2 SPI Clock Rate Select (SPR[2:0])—Bits 8, 1–0

The SPI clock rate select (SPR[2:0]) bits are used to program the divider of the Phi clock to generate a serial bit clock for the SPI peripheral when the SPI is configured as a master device. For an SPI configured as a slave, the serial clock is input from the master and these bits have no meaning. The SPR bits are cleared on hardware reset.

Table 7-1. SPR Divider Programming