Serial Peripheral Interface
SS
(to slave)
SCK (CPL=0)
SCK (CPL=1)
MOSI (from master)
MISO (from slave)
SS
(to slave)
SCK (CPL=0)
SCK (CPL=1)
MOSI (from master)
MISO (from slave)
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MSB |
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LSB |
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MSB |
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LSB |
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* Not defined, but normally MSB of word just received |
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AA1383 |
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Figure 7-3. SPI Transfer with CPH = 0
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MSB |
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LSB |
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MSB |
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LSB |
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* Not defined, but normally LSB of word previously transmitted |
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AA1384 |
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Figure 7-4. SPI Transfer with CPH = 1
7.2 SPI Programming Model
Each SPI peripheral provides the following registers:
•SPI control register (SPCR)
•SPI status register (SPSR)
•SPI data register (SPDR)
These registers are shown in Figure 7-5 on page 7-5. The descriptions of the registers in the following paragraphs apply equally to the corresponding registers on SPI0 and SPI1.
7-4 |
DSP56824 User’s Manual |
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SPI Programming Model
SPCR1— X:$FFE6 |
15 |
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SPCR0— X:$FFE2 |
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SPR |
SPIE |
SPE |
WOM |
MST |
CPL |
CPH |
SPR |
SPR |
SPI Control Register |
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* |
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2 |
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1 |
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Reset = $0000 |
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Read/Write |
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SPSR1— X:$FFE5 |
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SPSR0— X:$FFE1 |
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SPIF |
WC |
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MDF |
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SPI Status Register |
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* |
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OL |
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Reset = $0000 |
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Read-Only |
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SPDR1— X:$FFE4 |
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SPDR0— X:$FFE0 |
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High byte |
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Low byte |
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SPI Data Register |
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(Always reads as $00) |
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(Contains 8-bit data) |
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Reset = Uninitialized |
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Read/Write |
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* Indicates reserved bits, written as 0 for future compatibility
SPI Interrupt Vectors:
SPI1 Serial System
P:$0028
SPI0 Serial System
P:$002A
Enabling SPI Interrupts in the IPR:
SPI1: Set bit 12 to 1 in the IPR (X:$FFFB).
SPI0: Set bit 13 to 1 in the IPR (X:$FFFB).
AA0147
Figure 7-5. SPI Programming Model
NOTE:
To use SPI0, the CC[3:0] bits in the PCC register must be correctly set. To use SPI1, the CC[7:4] bits in the PCC register must be correctly set. See Section 7.5, “Configuring Port C for SPI Functionality,” for more information.
Serial Peripheral Interface |
7-5 |