Port B Programming Examples
5.3.4 Generating Interrupts on Port B
Example 5-4 shows how to configure and use Port B for generating interrupts.
Example 5-4. Generating Interrupts on Port B
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;* INTERRUPT example* |
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;* for Port B |
* |
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;* of DSP56824 chip * |
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;********************* |
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START |
EQU |
$0040 |
; Start of program |
BCR |
EQU |
$FFF9 |
; Bus Control Register |
IPR |
EQU |
$FFFB |
; Interrupt Priority Register |
PBD |
EQU |
$FFEC |
; Port B Data |
PBDDR |
EQU |
$FFEB |
; Port B Data Direction Register |
PBINT |
EQU |
$FFEA |
; Port B Interrupt Register |
data_o |
EQU |
$0000 |
; data output |
data_i |
EQU |
$0001 |
; data input |
;************** |
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;* Vector setup* |
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;************** |
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ORG |
P:$0000 |
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; Cold Boot |
JMP |
START |
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; also Hardware RESET vector (Mode 0, 1, 3) |
ORG |
P:$E000 |
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; Warm Boot |
JMP |
START |
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; Hardware RESET vector (Mode 2) |
ORG |
P:$0014 |
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; |
JSR |
GPIOISR |
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; GPIO Interrupt vector |
ORG |
P:START |
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; Start of program |
;************** |
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;* General setup* |
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;************** |
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MOVEP |
#$0000,X:BCR |
; External Program memory has 0 wait states. |
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; External data memory has 0 wait states. |
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; Port A pins are tri-stated when no |
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; external access occurs. |
BFCLR |
#$0200,SR |
; Allow IPL (Interrupt Priority Level) 0. |
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; -- Enable maskable interrupts. |
;* Port B setup* |
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; -- (peripherals, and so on);************** |
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;************** |
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MOVEP |
#$8000,X:PBINT |
; Enable GPIO interrupt requests for |
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; rising transitions on PB7. |
MOVEP |
#$FF00,X:PBDDR |
; Select PB0-PB7 as input, PB8-PB15 as output |
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BFSET |
#$8000,X:IPR |
; Enable GPIO interrupts. |
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;************** |
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;* Main routine* |
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;************** |
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; ... |
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MOVE |
#$0000,X:data_o |
; Initialize “data_o” |
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TESTPAT |
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; Test Pattern Loop |
MOVE |
X:data_o,X0 |
; Put bits 8-15 of “data_o” on pins PB8-PB15. |
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MOVEP |
X0,X:PBD |
; Bits going to input pins are ignored. |
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ADD |
#$0100,X0 |
; Change output pattern: increment by 1. |
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MOVE |
X0,X:data_o |
; Increment upper byte by 1. |
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MOVEP |
X:PBD,X0 |
; Read PB0-PB7 into bits 0-7 of “data_i”. |
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MOVE |
X0,X:data_i |
; Bits 8-15 get values of PB8-PB15 as well. |
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BRA |
TESTPAT |
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; ... |
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GPIOISR |
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; GPIO Interrupt Service Routine |
RTI |
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; interrupt code |
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Port B GPIO Functionality |
5-11 |
Port B GPIO Functionality
5-12 |
DSP56824 User’s Manual |
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Chapter 6
Port C GPIO Functionality
The peripheral communications port (Port C) provides 16 multiplexed programmable I/O pins. These pins may be used as general-purpose input/output (GPIO) pins or allocated to on-chip peripherals—a timer module, two serial peripheral interfaces (SPIs), and a synchronous serial interface (SSI). (See Figure 6-1 on page 6-2.) Each pin is individually programmable.
This section describes how to program the pins for Port C and provides general information about their use as GPIO pins. Specifics for programming the various peripherals represented on Port C are provided in the appropriate sections, as follows:
•SPI module programming specifics are located in Chapter 7, “Serial Peripheral Interface.”
•SSI module programming specifics are located in Chapter 8, “Synchronous Serial Interface.”
•Timer module programming specifics are located in Chapter 9, “Timers.”
The Port C I/O interfaces are intended to minimize system chip count and “glue” logic in many DSP applications. Each I/O interface has its own control, status, and data registers that are treated as memory-mapped peripheral registers by the DSP56824. Each interface has several dedicated interrupt vector addresses and control bits to enable or disable interrupts. This minimizes the overhead associated with servicing the device, since each interrupt source may have its own service routine.
Port C GPIO Functionality |
6-1 |
Port C GPIO Functionality
External
Address MUX
External
Data Switch
Bus Control
General-
Purpose
I/O
Peripheral
Communications
Interfaces
SPI (x2)
SSI
Timers
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Alternate |
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Function |
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Function |
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A15–A0 |
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D15–D0 |
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RD |
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WR |
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PS |
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DS |
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PB0 |
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PB1 |
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PB2 |
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PB3 |
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PB4 |
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PB5 |
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PB6 |
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PB7 |
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PB8 |
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PB9 |
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PB10 |
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PB11 |
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PB12 |
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PB13 |
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PB14 |
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XCOLF |
/PB15 |
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PC0 |
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MISO0 |
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PC1 |
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MOSI0 |
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PC2 |
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SCK0 |
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PC3 |
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SS0 |
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PC4 |
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MISO1 |
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PC5 |
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MOSI1 |
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PC6 |
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SCK1 |
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PC7 |
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SS1 |
Port C |
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PC8 |
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STD |
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PC9 |
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SRD |
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PC10 |
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STCK |
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PC11 |
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STFS |
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PC12 |
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SRCK |
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PC13 |
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SRFS |
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PC14 |
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TIO01 |
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PC15 |
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TIO2 |
AA0137 |
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Figure 6-1. DSP56824 Input/Output Block Diagram
6-2 |
DSP56824 User’s Manual |
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