List of Examples

Example 1-1 On-Chip and Off-Chip Instruction Fetches . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 Example 3-1 Breaking a Read Instruction in Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Example 5-1 Receiving Data on Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Example 5-2 Sending Data on Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Example 5-3 Loop-Back Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Example 5-4 Generating Interrupts on Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Example 6-1 Receiving Data on Port C GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 Example 6-2 Sending Data on Port C GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 Example 6-3 Loop-Back Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 Example 7-1 Configuring an SPI Port as Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14 Example 7-2 Configuring an SPI Port as Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16 Example 7-3 Sending Data from Master to Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 Example 9-1 Counting Events on a Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 Example 9-2 Decrementing to Zero and Generating an Interrupt . . . . . . . . . . . . . . . . . . . . . 9-11 Example 9-3 Timer Using 25% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 Example 10-1 Programming the PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-12 Example 11-1 Sending a COP Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-9 Example 12-1 Display a Specified Register—Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-51 Example 12-2 Display X Memory Area from Address xxxx—Serial . . . . . . . . . . . . . . . . . . 12-52 Example 12-3 Return from Debug Mode to Normal Mode—Serial . . . . . . . . . . . . . . . . . . . 12-53 Example 12-4 Begin Debug Activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-54 Example 12-5 Display a Specified Register—OnCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-56 Example 12-6 Display X Memory Area from Address xxxx—OnCE. . . . . . . . . . . . . . . . . . 12-56 Example 12-7 Returning from Debug Mode to Normal Mode—OnCE . . . . . . . . . . . . . . . . 12-58 Example 12-8 Jump to a New Program—Go from Address $xxxx. . . . . . . . . . . . . . . . . . . . 12-58 Example A-1 DSP56824 Bootstrap Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4 Example B-1 DSP56824 BSDL Listing—100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1

About This Book

This manual describes the DSP56824 16-bit digital signal processor (DSP), its memory and operating modes, and its peripheral modules. This manual is intended to be used with the DSP56800 Family Manual (DSP56800FM/AD), which describes the CPU, programming models, and instruction set details. The DSP56824 Technical Data Sheet (DSP56824/D) provides electrical specifications as well as timing, pinout, and packaging descriptions.

Audience

The information in this manual is intended to assist design and software engineers with integrating the DSP56824 digital signal processor into a design and with developing application software.

Organization

Information in this manual is organized into chapters by topic. The contents of the chapters are as follows:

Chapter 1, “DSP56824 Overview.” This section provides a brief overview of the DSP56824.

Chapter 2, “Signal Descriptions.” This section provides a description of the pins on the DSP56824 chip and how the pins are grouped into the various interfaces.

Chapter 3, “Memory Configuration and Operating Modes.” This section describes the on-chip memory, structures, registers, and interfaces.

Chapter 4, “External Memory Interface.” This section describes the DSP56824 external memory interface, which is also referred to as Port A.

Chapter 5, “Port B GPIO Functionality.” This section describes the dedicated general-purpose input/output (GPIO) interface, which is also referred to as Port B.

Chapter 6, “Port C GPIO Functionality.” This section describes the 16 dual-function pins that constitute Port C and defines their GPIO functions. Chapters 7–9 describe these pins’ alternate functionality.

Chapter 7, “Serial Peripheral Interface.” This section describes the serial peripheral interface (SPI), which is a part of Port C and which communicates with external devices, such as liquid crystal displays (LCDs) and microcontroller units (MCUs).

Chapter 8, “Synchronous Serial Interface.” This section describes the synchronous serial interface (SSI), which is a part of Port C and which communicates with devices such as codecs, other DSPs, microprocessors, and peripherals to provide the primary data input path.

Chapter 9, “Timers.” This section describes the three internal timer/counter devices that are a part of Port C.

Chapter 10, “On-Chip Clock Synthesis.” This section describes the internal oscillator, phase lock loop (PLL), and timer distribution chain for the DSP56824.

Chapter 11, “COP and RTI Module.” This section describes the on-chip watchdog timer and the real-time interrupt generator.

Chapter 12, “OnCE™ Module.” This section describes the specifics of the DSP56824’s On-Chip Emulation (OnCE™ ) module, which is accessed through the Joint Test Action Group (JTAG) port.

Chapter 13, “JTAG Port.” This section describes the specifics of the DSP56824’s JTAG port.

Appendix A, “Bootstrap Program.” This section provides a sample listing of bootstrap code that can be used to start or reset the DSP56824.

Appendix B, “Boundary Scan Description Language Listing.” This section provides the Boundary Scan Description Language (BSDL) listing for the DSP56824.

Appendix C, “Programmer’s Sheets.” This section provides programming references and master programming sheets used to program the DSP56824 registers.

Suggested Reading

A list of DSP-related books is included here as an aid for the engineer who is new to the field of DSP:

Advanced Topics in Signal Processing, Jae S. Lim and Alan V. Oppenheim (Prentice-Hall: 1988).

Applications of Digital Signal Processing, A. V. Oppenheim (Prentice-Hall: 1978).

Digital Processing of Signals: Theory and Practice, Maurice Bellanger (John Wiley and Sons: 1984).

Digital Signal Processing, Alan V. Oppenheim and Ronald W. Schafer (Prentice-Hall: 1975).

Digital Signal Processing: A System Design Approach, David J. DeFatta, Joseph G. Lucas, and William S. Hodgkiss (John Wiley and Sons: 1988).

Discrete-Time Signal Processing, A. V. Oppenheim and R.W. Schafer (Prentice-Hall: 1989).

Foundations of Digital Signal Processing and Data Analysis, J. A. Cadzow (Macmillan: 1987).

Handbook of Digital Signal Processing, D. F. Elliott (Academic Press: 1987).

Introduction to Digital Signal Processing, John G. Proakis and Dimitris G. Manolakis (Macmillan: 1988).

Multirate Digital Signal Processing, R. E. Crochiere and L. R. Rabiner (Prentice-Hall: 1983).

Signal Processing Algorithms, S. Stearns and R. Davis (Prentice-Hall: 1988).

Signal Processing Handbook, C. H. Chen (Marcel Dekker: 1988).

Signal Processing: The Modern Approach, James V. Candy (McGraw-Hill: 1988).

Theory and Application of Digital Signal Processing, Lawrence R. Rabiner and Bernard Gold (Prentice-Hall: 1975).

Conventions

The following conventions are used in this manual:

•Bits within registers are always listed from most significant bit (MSB) to least significant bit (LSB).

•Bits within a register are formatted AA[n:0] when more than one bit is involved in a description. For purposes of description, the bits are presented as if they are contiguous within a register. However, this is not always the case. Refer to the programming model diagrams or to the programmer’s sheets to see the exact location of bits within a register.

•When a bit is described as “set,” its value is set to 1. When a bit is described as “cleared,” its value is set to 0.

•Pins or signals that are asserted low (made active when pulled to ground) have an overbar over their name. For example, the SS0 pin is asserted low.

•Hex values are indicated with a dollar sign ($) preceding the hex value, as follows: $FFFB is the X memory address for the Interrupt Priority Register (IPR).

•Code examples are displayed in a monospaced font, as follows:

•Pins or signals listed in code examples that are asserted low have a tilde in front of their names. In the previous example, line 3 refers to the SS0 pin (shown as ~SS0).

•The word “reset” is used in three different contexts in this manual. There are a reset pin that is always written as RESET, the processor state occurring when the RESET pin is asserted that is always written as Reset, and the word reset that refers to the reset function and is written in lowercase (without the italics that are used here for emphasis) or with a leading capital letter as style dictates, such as in headings and captions. The word “pin” is a generic term for any pin on the chip.

•The word assert means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. The word deassert means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC.

1.Ground is an acceptable low voltage level. See the appropriate data sheet for the range of acceptable low voltage levels (typically a TTL logic low).

2.VCC is an acceptable high voltage level. See the appropriate data sheet for the range of acceptable high voltage levels (typically a TTL logic high).

Definitions, Acronyms, and Abbreviations

The following terms appear frequently in this manual:

References

Please consult the following for more information on the function and characteristics of the DSP56824 digital signal processor.

•DSP56800 Family Manual (order number DSP56800FM/D)

•DSP56824 Technical Data Sheet (order number DSP56824/D)

These documents, as well as Motorola’s DSP development tools, can be obtained through a local Motorola Semiconductor Sales Office or authorized distributor. To receive the latest information, access the Motorola DSP home page located at http://www.motorola-dsp.com.

Chapter 1

DSP56824 Overview

The DSP56824 is a member of the family of DSPs based on the DSP56800 core. This general-purpose DSP combines processing power with configuration flexibility, making it an excellent, cost-effective solution for signal processing and control functions. To achieve its design goals, the DSP56824 uses an efficient MPU-style general-purpose 16-bit DSP core, program and data memories, and support circuitry.

The CPU (the DSP56800 core) consists of three execution units operating in parallel, allowing as many as six operations during each instruction cycle. The MPU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C Compilers.

The DSP56824 supports program execution from internal or external memories. Two data operands can be accessed per instruction cycle from the on-chip data RAM. The programmable peripherals and ports provide support for interfacing multiple external devices, such as codecs, microprocessors, or other DSPs. The DSP56824 also provides 16 to 32 general-purpose input/output (GPIO) lines, depending on how peripherals are configured, and 2 external dedicated interrupt lines. Because of its configuration flexibility, compact program code, and low cost, the DSP56800 core family is well suited for cost-sensitive applications, including digital wireless messaging, digital answering machines and feature phones, wireline and wireless modems, servo and AC motor control, and digital cameras.