Port A Description

4.2 Port A Description

The external memory interface (also referred to as Port A) is the port through which all accesses to external memories and external memory-mapped peripherals are made. This port contains a 16-bit address bus, a 16-bit data bus, and four bus control pins for strobes. The external memory interface uses one programmable register for bus control, the bus control register (BCR).

External memory can be accessed at the maximum speed of the bus unit. In addition, software-controlled wait states can be introduced when accessing slower memories or peripherals. Wait states are programmable using registers. Figure 4-3 and Figure 4-4 on page 4-5 show examples of bus cycles with and without wait states.

4.2.1 Bus Control Register (BCR)

The bus control register (BCR), located at X:$FFF9, is a 16-bit read/write register used for inserting software wait states on accesses to external program or data memory. Two 4-bit wait state fields are provided, each capable of specifying from 0 to 15 wait states. On processor reset, each wait state field is set to $F so that 15 wait states are inserted, allowing slower memory to be used immediately after reset. All other BCR bits are cleared on processor reset.

Figure 4-2. BCR Programming Model

4.2.1.1 Reserved Bits—Bits 15–10

Bits 15–10 are reserved and are read as zero during read operations. These bits should be written with zero to ensure future compatibility.

4.2.1.2 Drive (DRV)—Bit 9

The Drive (DRV) control bit is used to specify what occurs on the external memory port pins when no external access is performed—whether the pins remain driven or are placed in tri-state. Table 4-2 on page 4-6 and Table 4-3 on page 4-7 summarize the action of the DRV bit. The DRV bit is cleared on hardware reset.

4.2.1.3 Reserved Bit—Bit 8

Bit 8 is reserved and is read as zero during read operations. This bit should be written with zero to ensure future compatibility.

External Memory Interface

4.2.1.4 Wait State X Data Memory (WSX[3:0])—Bits 7–4

The wait state X data memory (WSX[3:0]) control bits allow for the programming of the wait states for external X data memory. Table 4-1 shows the wait states provided with these bits. The WSX[3:0] and the WSP[3:0] bits are programmed in the same fashion but do not need to be set to the same value.

Table 4-1. Programming WSP[3:0] and WSX[3:0] Bits for Wait States

4.2.1.5 Wait State P Memory (WSP[3:0])—Bits 3–0

The wait state program memory (WSP[3:0]) control bits allow for the programming of the wait states for external program memory. These bits are programmed as shown in Table 4-1.

Figure 4-3 on page 4-5 shows an example of bus cycles without wait states, and Figure 4-4 on page 4-5 shows an example of bus cycles with wait states. For more information on wait states, see the DSP56824 Technical Data Sheet.

Port A Description

CLKO

A15–A0

PS, DS

WR

RD

AA0130

Figure 4-3. Bus Operation (Read/Write—Zero Wait States)

T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 Tw T2 Tw T2 Tw T2 T3 T0 T1

CLKO

A15–A0

PS, DS

WR

RD

AA0133

Figure 4-4. Bus Operation (Read/Write—Three Wait States)