3.3.2 Interrupt Priority Structure

Priority

Exception

IPR Bits

Level 1 (Non-maskable)

Highest

Hardware

RESET

—

COP timer RESET

—

Illegal instruction trap

—

Hardware stack overflow

—

OnCE module instruction trap

—

Lower

SWI

—

Level 0 (Maskable)

Higher

IRQA

(external interrupt)

2, 1

(external interrupt)

5, 4

IRQB

Channel 6 peripheral interrupt— SSI

9

Channel 5 peripheral interrupt— Reserved

10

Channel 4 peripheral interrupt— Timer module

11

Channel 3 peripheral interrupt— SPI1

12

Channel 2 peripheral interrupt— SPI0

13

Channel 1 peripheral interrupt— Real-time timer

14

Lowest

Channel 0 peripheral interrupt— Port B GPIO

15

Table 3-7. Reset and Interrupt Vector Map

Interrupt Starting Address

IPL

Interrupt Source

$0000/$7F801/$E0002

—

Hardware

RESET

$0000/$7F821/$E0022

—

COP timer RESET

$0004

—

(Reserved)

$0006

1

Illegal instruction trap

$0008

1

Software interrupt (SWI)

$000A

1

Hardware stack overflow

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DSP56824 User’s Manual

DSP56824 Reset and Interrupt Vectors

Table 3-7. Reset and Interrupt Vector Map (Continued)

Interrupt Starting Address

IPL

Interrupt Source

$000C

1

OnCE module instruction trap

$000E

1

(Reserved)

$0010

0

IRQA

$0012

0

IRQB

$0014

0

Port B GPIO interrupt

$0016

0

Real-time interrupt

$0018

0

Timer 0 overflow

$001A

0

Timer 1 overflow

$001C

0

Timer 2 overflow

$001E

0

(Reserved)

$0020

0

SSI receive data with exception status

$0022

0

SSI receive data

$0024

0

SSI transmit data with exception status

$0026

0

SSI transmit data

$0028

0

SPI1 serial system

$002A

0

SPI0 serial system

$002C

0

Available for program code

.

.

$007E

0

Memory Configuration and Operating Modes

3-17

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DSP56824 User’s Manual