Memory Configuration and Operating Modes

3.3 DSP56824 Reset and Interrupt Vectors

The interrupt vector map specifies the address to which the processor jumps when it recognizes an interrupt or encounters a reset condition. The instruction located at this address must be a jump to subroutine (JSR) instruction for an interrupt or for a reset. The interrupt vector map for a given chip is specified by all possible interrupt sources on the DSP56800 core, as well as from the peripherals. No interrupt priority level (IPL) is specified for hardware reset (assertion of the RESET pin) or for COP reset because these conditions reset the chip, and a reset takes precedence over all other interrupts.

Table 3-6 on page 3-16 provides the interrupt priority structure for the DSP56824, including on-chip peripherals. Table 3-7 on page 3-16 lists the reset and interrupt vectors for the DSP56824. A full description of interrupts is provided in the DSP56800 Family Manual.

NOTE:

In Mode 2, the hardware and COP reset vectors are both located at address $E000 in external memory. In Mode 1, the hardware reset vector is located at address $7F80 and the COP reset vector is at $7F82. In Modes 0 and 3, the hardware reset vector is at $0000 and the COP reset vector is at $0002.

3.3.1 DSP56824 Interrupt Priority Register (IPR)

The interrupt priority register (IPR) is a read/write memory-mapped register located at X:$FFFB. The IPR specifies the IPL for each of the interrupting devices, including the IRQA and IRQB pins, as well as each on-chip peripheral capable of generating interrupts. The interrupt arbiter on the DSP56800 core contains seven interrupt channels for use by peripherals, in addition to the IRQ interrupts and the interrupts provided by the core. The IPL for each on-chip peripheral device (interrupt channels 0–6) and for each external source (IRQA and IRQB) can be individually enabled or disabled under software control. In addition, the IPR specifies the trigger mode of each external interrupt source and can enable or disable the individual external interrupts. The IPR is cleared on hardware reset.

Peripheral interrupts are enabled or masked by writing to the IPR after enabling them using the SR. Table 3-6 on page 3-16 shows the interrupt priority order. Figure 3-5 on page 3-15 shows the IPR, and Figure 3-6 on page 3-15 shows how the IPR bits are programmed. Unused bits are read as zero and should be written with zero to ensure future compatibility.

DSP56824 Reset and Interrupt Vectors

Figure 3-6. Interrupt Programming

NOTE:

To avoid spurious interrupts, it may be necessary to disable IRQx interrupts (by clearing the IxL0 bit) before modifying IxL1 or IxINV.

If the trigger mode is programmed to be edge sensitive in the IPR and the chip enters stop mode, one of two things could happen:

1.A valid level-sensitive value on the interrupt pin will bring the chip out of stop mode. The chip executes the next instruction following the STOP instruction; the interrupt service routine will not be executed.

2.A valid edge-sensitive interrupt will exit the chip from stop mode as well as service the interrupt by executing the interrupt service routine.