Memory Configuration and Operating Modes
interrupts have IPL 0. To enable these interrupts, first selectively enable all desired interrupts for each peripheral using the IPR. After enabling the interrupts, set the I[1:0] bits in the SR to 01. This should be done for all applications that use the on-chip peripherals. See Section 3.3.1, “DSP56824 Interrupt Priority Register (IPR),” for more information on the IPR.
Table 3-3 shows the valid values to use for initializing the SR, the values for the interrupt mask bits, and the interrupt masking.
Table 3-3. Interrupt Mask Bit Definition
Value of SR |
I[1:0] |
Exceptions Permitted |
Exceptions Masked |
|
|
|
|
|
|
|
|
(Reserved) |
00 |
(Reserved) |
(Reserved) |
|
|
|
|
$0100 |
01 |
IPL 0, 1 |
None |
|
|
|
|
(Reserved) |
10 |
(Reserved) |
(Reserved) |
|
|
|
|
$0300 (reset value) |
11 |
IPL 1 |
IPL 0 |
|
|
|
|
NOTE:
Unless IPL 0 interrupts are enabled for on-chip peripheral interrupts in the
SR, setting the IPR will have no effect.
For best results, use the following command to enable peripheral interrupts (IPL 0) in the SR:
BFCLR #$0200,SR
This command changes the I[1:0] bits from 11 to 01, clearing only the I1 bit and leaving all other bits in the SR unaffected. If it is necessary to temporarily disable peripheral interrupts, issue the following command:
BFSET #$0200,SR
This command changes the I[1:0] bits from 01 to 11, disabling all the peripheral interrupts. Afterwards, re-enable interrupts using the BFCLR #$0200,SR command.
3.1.4 On-Chip Peripheral Memory Map
Table 3-4 shows the on-chip memory-mapped I/O registers on the DSP56824.
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Table 3-4. X I/O Registers |
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|
Address |
Register |
|
|
|
|
X:$FFFF |
OPGDBR— OnCE PGDB bus transfer register |
|
|
X:$FFFE |
(Reserved) * |
|
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X:$FFFD |
(Reserved) * |
|
|
X:$FFFC |
(Reserved) * |
|
|
X:$FFFB |
IPR— interrupt priority register |
|
|
X:$FFFA |
(Reserved) * |
|
|
X:$FFF9 |
BCR— bus control register (Port A) |
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3-8 |
DSP56824 User’s Manual |
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DSP56824 Memory Map
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Table 3-4. X I/O Registers (Continued) |
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|
Address |
Register |
|
|
|
|
X:$FFF8 |
(Reserved) * |
|
|
X:$FFF7 |
(Reserved) * |
|
|
X:$FFF6 |
(Reserved) * |
|
|
X:$FFF5 |
(Reserved) * |
|
|
X:$FFF4 |
(Reserved) * |
|
|
X:$FFF3 |
PCR1— PLL control register 1 |
|
|
X:$FFF2 |
PCR0— PLL control register 0 |
|
|
X:$FFF1 |
COPCTL— COP/RTI control register |
|
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X:$FFF0 |
COPCNT— COP/RTI count register (read-only) |
|
COPRST— COP reset register (write-only) |
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X:$FFEF |
PCD— Port C data register |
|
|
X:$FFEE |
PCDDR— Port C data direction register |
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X:$FFED |
PCC— Port C control register |
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X:$FFEC |
PBD— Port B data register |
|
|
X:$FFEB |
PBDDR— Port B data direction register |
|
|
X:$FFEA |
PBINT— Port B interrupt register |
|
|
X:$FFE9 |
(Reserved) * |
|
|
X:$FFE8 |
(Reserved) * |
|
|
X:$FFE7 |
(Reserved) * |
|
|
X:$FFE6 |
SPCR1— SPI1 control register |
|
|
X:$FFE5 |
SPSR1— SPI1 status register |
|
|
X:$FFE4 |
SPDR1— SPI1 data register |
|
|
X:$FFE3 |
(Reserved) * |
|
|
X:$FFE2 |
SPCR0— SPI0 control register |
|
|
X:$FFE1 |
SPSR0— SPI0 status register |
|
|
X:$FFE0 |
SPDR0— SPI0 data register |
|
|
X:$FFDF |
TCR01— Timer 0 and 1 control register |
|
|
X:$FFDE |
TPR0— Timer 0 preload register |
|
|
X:$FFDD |
TCT0— Timer 0 count register |
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Memory Configuration and Operating Modes |
3-9 |
Memory Configuration and Operating Modes
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Table 3-4. X I/O Registers (Continued) |
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|
Address |
Register |
|
|
|
|
X:$FFDC |
TPR1— Timer 1 preload register |
|
|
X:$FFDB |
TCT1— Timer 1 count register |
|
|
X:$FFDA |
TCR2— Timer 2 control register |
|
|
X:$FFD9 |
TPR2— Timer 2 preload register |
|
|
X:$FFD8 |
TCT2— Timer 2 count register |
|
|
X:$FFD7 |
(Reserved) * |
|
|
X:$FFD6 |
(Reserved) * |
|
|
X:$FFD5 |
STSR— SSI time slot register |
|
|
X:$FFD4 |
SCRRX— SSI receive control register |
|
|
X:$FFD3 |
SCRTX— SSI transmit control register |
|
|
X:$FFD2 |
SCR2— SSI control register 2 |
|
|
X:$FFD1 |
SCSR— SSI control/status register |
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|
X:$FFD0 |
SRX— SSI receive register (read-only) |
|
STX— SSI transmit register (write-only) |
|
|
X:$FFCF |
(Reserved) * |
|
|
X:$FFCE |
(Reserved) * |
|
|
X:$FFCD |
(Reserved) * |
|
|
X:$FFCC |
(Reserved) * |
|
|
X:$FFCB |
(Reserved) * |
|
|
X:$FFCA |
(Reserved) * |
|
|
X:$FFC9 |
(Reserved) * |
|
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X:$FFC8 |
(Reserved) * |
|
|
X:$FFC7 |
(Reserved) * |
|
|
X:$FFC6 |
(Reserved) * |
|
|
X:$FFC5 |
(Reserved) * |
|
|
X:$FFC4 |
(Reserved) * |
|
|
X:$FFC3 |
(Reserved) * |
|
|
X:$FFC2 |
(Reserved) * |
|
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DSP56824 User’s Manual |
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