DSP56824 Memory Map

If both the NL and LF bits are set (that is, two DO loops are active) and a DO instruction is executed, a hardware stack overflow interrupt occurs because there is no more space on the HWS to support a third DO loop.

The NL bit is also affected by any accesses to the HWS. Any MOVE instruction that writes this register copies the old contents of the LF bit into the NL bit and then sets the LF bit. Any reads of this register, such as from a MOVE or TSTW instruction, copy the NL bit into the LF bit and then clear the NL bit.

3.1.2.2 Reserved Bits—Bits 14–9

The OMR bits 14–9 are reserved. They are read as zero during DSP read operations and should be written with zero to ensure future compatibility.

3.1.2.3 Condition Codes (CC)—Bit 8

The condition code (CC) bit selects whether condition codes are generated using a 36-bit result from the multiply-accumulator (MAC) array or a 32-bit result. When the CC bit is set, the C, N, V, and Z condition codes are generated based on bit 31 of the data arithmetic logic unit (data ALU) result. When cleared, the C, N, V, and Z condition codes are generated based on bit 35 of the data ALU result. The generation of the L, E, and U condition codes are not affected by the CC bit. The CC bit is cleared by processor reset.

NOTE:

The unsigned condition tests used when branching or jumping (HI, HS, LO, or LS) can be used only when the condition codes are generated with the CC bit set. Otherwise, the chip does not generate the unsigned conditions correctly.

3.1.2.4 Reserved Bit—Bit 7

The OMR bit 7 is reserved. It is read as zero during DSP read operations and should be written with zero to ensure future compatibility.

3.1.2.5 Stop Delay (SD)—Bit 6

The stop delay (SD) bit selects the delay that the DSP needs to exit the stop mode. When the SD bit is set, the processor exits quickly from stop mode. When the SD bit is cleared, the processor exits slowly from stop mode. Specific time intervals for stop delay are provided in the DSP56824 Technical Data Sheet. The SD bit is cleared by processor reset.

3.1.2.6 Rounding (R)—Bit 5

The rounding (R) bit selects between two’s-complement rounding and convergent rounding. When the R bit is set, two’s-complement rounding (always round up) is used. When the R bit is cleared, convergent rounding is used. The two rounding modes are discussed in detail in the DSP56800 Family Manual. The R bit is cleared by processor reset.