Memory Configuration and Operating Modes

3.1.2 Operating Mode Register (OMR)

The operating mode register (OMR) is a 16-bit register that defines the current chip operating mode of the processor. The OMR bits are affected by processor reset, operations on the hardware stack (HWS), and instructions that directly reference the OMR. A nested DO loop also affects the OMR.

During processor reset, the chip operating mode bits (MA and MB) are loaded from the external mode select pins MODA and MODB, respectively. The OMR programming model is shown in Figure 3-3 and is described in the following subsections.

NOTE:

When a bit of the OMR is changed by an instruction, a delay of one instruction cycle is necessary before the new mode comes into effect.

NL— Nested Looping

CC— Condition Codes

SD— Stop Delay

R— Rounding

SA— Saturation Mode

EX— External X Memory

MA, MB— Operating Mode

Figure 3-3. Operating Mode Register (OMR) Programming Model

3.1.2.1 Nested Looping (NL)—Bit 15

The nested looping (NL) bit displays the status of program DO looping and the hardware stack. When the NL bit is set, it indicates that the program is currently in a nested DO loop (that is, two DO loops are active). When this bit is cleared, it indicates that the program is currently not in a nested DO loop—there may be a single active DO loop or no DO loop active. This bit is necessary for saving and restoring the contents of the hardware stack. REP looping does not affect this bit.

It is important that the user never puts the processor in the reserved combination specified in Table 3-1. This can be avoided by ensuring that the LF bit is never cleared when the NL bit is set. The NL bit is cleared on processor reset.