JTAG Port

There are two paths through the 16-state machine. The Shift-IR-Scan path captures and loads JTAG instructions into the JTAG IR. The Shift-DR-Scan path captures and loads data into the other JTAG registers. The TAP controller executes the last instruction decoded until a new instruction is entered at the Update-IR state or until the test-logic-reset state is entered. When the JTAG port is used to access OnCE module registers, accesses are first enabled by shifting the ENABLE_ONCE instruction into the JTAG IR. After this is selected, the OnCE module registers and commands are read and written through the JTAG pins using the Shift-DR-Scan path. Asserting the JTAG’s TRST pin asynchronously forces the JTAG state machine into the test-logic-reset state.

13.4 DSP56824 Restrictions

The TRST pin shares functionality with the DE output function of the OnCE module. This implementation is not fully compliant with the JTAG standard. The function of this pin is controlled by the OnCE control register (OCR). The 2 bits in the OCR that determine how the pin functions, DE and DRM, are cleared on RESET assertion, forcing the TRST/DE pin to its input JTAG reset function. The bits may be set either by an explicit write to the OCR, which involves a lengthy serial sequence, or on power up. To guarantee that TRST functions as a JTAG reset, it is recommended that both TRST and RESET be asserted at least once after powering up.

The control afforded by the output enable signals using the BSR and the EXTEST instruction requires a compatible circuit-board test environment to avoid device-destructive configurations. The user must avoid situations in which the DSP56824 output drivers are enabled into actively driven networks.

During power up, the TRST pin must be externally asserted to force the TAP controller into this state. After powering up is concluded, TMS must be sampled as a logic one for five consecutive TCK rising edges. If TMS either remains unconnected or is connected to VDD, then the TAP controller cannot leave the test-logic-reset state, regardless of the state of TCK.

The DSP56824 features a low-power stop mode that is invoked using the STOP instruction. JTAG interaction with low-power stop mode is as follows:

1.The TAP controller must be in the test-logic-reset state to either enter or remain in stop mode. Leaving the TAP controller test-logic-reset state negates the ability to achieve low power but does not otherwise affect device functionality.

2.The TCK input is not blocked in low-power stop mode. To consume minimal power, the TCK input should be externally connected to VDD or ground.

3.The TMS and TDI pins include on-chip pull-up resistors. In low-power stop mode, these two pins should remain either unconnected or connected to VDD to achieve minimal power consumption.

Since all DSP56824 clocks are disabled during stop state, the JTAG interface provides the means of polling the device status (sampled in the Capture-IR state).

Appendix A

Bootstrap Program

This section describes the bootstrap program contained in the DSP56824 program ROM. This program can load the on-chip program RAM from an external memory through the external memory interface (Port A) or from the serial peripheral interface 0 (SPI0), and then transfer program control to a starting address in program RAM.

The program RAM locations that are available for loading are the 128 internal program RAM locations from P:$0000 to P:$007F, or the 32K of external program RAM locations from P:$8000 to P:$FFFF. It is not possible to load any external program RAM locations from P:$0000 to P:$7FFF as these are only accessible in Mode 3. Figure 3-1 on page 3-2 provides a picture of the DSP56824 memory map.

The bootstrap program begins at P:$7F80, which is the Mode 1 reset vector location. The following sequence describes the bootstrap program flow.

1.External memory location P:$C000 is read to determine the source of the data to load into program RAM. If bit 15 (D[15]) of P:$C000 is zero, program RAM is loaded with values read through SPI0. If bit 15 (D[15]) is one, program RAM is loaded with values received through the lower byte of Port A.

2.Once the program determines the bootstrap source, data is read from that source. The first word (2 bytes) read contains the number of program words that are loaded. The second word (also 2 bytes) contains the starting address to which the program words are loaded; this address is also where program control is transferred to after exiting the bootstrap program. The least significant byte of each word should be transmitted first, followed by the most significant byte.

3.After the bootstrap program determines the number of words and the starting address, the remaining words are loaded byte-wise into contiguous program RAM. This continues until the specified number of words have been loaded.

4.When the loading of the program RAM has completed, the bootstrap program terminates and transfers program control to the starting address. At this point, the program the user has downloaded begins to execute.

NOTE:

This routine loads data starting with the least significant byte.