Serial Peripheral Interface (SPI) Signals

Table 2-10. Dedicated GPIO Signals

Signal

State

Signal Name

During

Signal Description

Type

Reset

PB8–PB14

Input or

Input

Port B GPIO— These eight pins are dedicated GPIO pins that can

output

individually be programmed as input or output pins.

After reset, the default state is GPIO input.

Input

Input,

— During reset, the External Crystal Oscillator Low Frequency

XCOLF

XCOLF

pulled

is tied to an

(XCOLF)

function of this pin is active. PB15/XCOLF

high

on-chip pull-up transistor that is active during reset. When

XCOLF

is

internally

driven low during reset (or tied to a 10 kΩ pull-down resistor), the crys-

tal oscillator amplifier is set to the low frequency mode. In this low fre-

quency mode, only oscillator frequencies of 32 kHz and 38.4 kHz are

supported. If

XCOLF

is not driven low during reset (or if a pull-down

resistor is not used), the crystal oscillator amplifier operates in the

default mode, and oscillator frequencies from 2 MHz to 10 MHz are

supported. If an external clock is provided to the EXTAL pin, 70 MHz is

the maximum frequency allowed. (In this case, do not connect a

pull-down resistor or drive this pin low during reset.)

When the low frequency mode is selected, EXTAL is in phase with

Phi1, T1, and T3. When the default mode is selected, EXTAL is in

phase with CLKO, Phi0, T0, and T2.

PB15

Input or

Port B GPIO— This pin is a dedicated GPIO pin that can individu-

output

ally be programmed as an input or output pin.

After reset, the default state is GPIO input.

is not resam-

XCOLF

pled for Computer Operating Properly (COP) reset.

Signal

State

Signal Name

During

Signal Description

Type

Reset

MISO0

Input/

Input

SPI0 Master In/Slave Out (MISO0)— This serial data pin is an

output

input to a master device and an output from a slave device. The

MISO0 line of a slave device is placed in the high-impedance state

if the slave device is not selected. The driver on this pin can be

configured as an open-drain driver by the SPI’s Wired-OR mode

(WOM) bit when this pin is configured for SPI operation.

PC0

Input or

Port C GPIO 0 (PC0)— This pin is a GPIO pin called PC0 when the

output

SPI MISO0 function is not being used.

After reset, the default state is GPIO input.

Signal Descriptions

2-7

Signal

State

Signal Name

During

Signal Description

Type

Reset

MOSI0

Input/

Input

SPI0 Master Out/Slave In (MOSI0)— This serial data pin is an out-

output

put from a master device and an input to a slave device. The mas-

ter device places data on the MOSI0 line a half-cycle before the

clock edge that the slave device uses to latch the data. The driver

on this pin can be configured as an open-drain driver by the SPI’s

WOM bit when this pin is configured for SPI operation.

PC1

Input or

Port C GPIO 1 (PC1)— This pin is a GPIO pin called PC1 when the

output

SPI MOSI0 function is not being used.

After reset, the default state is GPIO input.

SCK0

Input/

Input

SPI0 Serial Clock (SCKO)— This bidirectional pin provides a serial

output

bit rate clock for the SPI. This gated clock signal is an input to a

slave device and is generated as an output by a master device.

Slave devices ignore the SCK signal unless the

SS

pin is active

low. In both master and slave SPI devices, data is shifted on one

edge of the SCK signal and is sampled on the opposite edge

where data is stable. The driver on this pin can be configured as an

open-drain driver by the SPI’s WOM bit when this pin is configured

for SPI operation. When using Wired-OR mode, the user must pro-

vide an external pull-up device.

PC2

Input or

Port C GPIO 2 (PC2)— This pin is a GPIO pin called PC2 when the

output

SPI SCK0 function is not being used.

After reset, the default state is GPIO input.

Input

Input

SPI0 Slave Select

— This input pin selects a slave device

SS0

(SS0)

before a master device can exchange data with the slave device.

SS

must be low before data transactions and must stay low for the

duration of the transaction. The

SS

line of the master must be held

high.

PC3

Input or

Port C GPIO 3 (PC3)— This pin is a GPIO pin called PC3 when the

output

SPI

SS0

function is not being used.

After reset, the default state is GPIO input.

MISO1

Input/

Input

SPI1 Master In/Slave Out (MISO1)— This serial data pin is an

output

input to a master device and an output from a slave device. The

MISO1 line of a slave device is placed in the high-impedance state

if the slave device is not selected. The driver on this pin can be

configured as an open-drain driver by the SPI’s WOM bit when this

pin is configured for SPI operation.

PC4

Input or

Port C GPIO 4 (PC4)— This pin is a GPIO pin called PC4 when the

output

SPI MISO1 function is not being used.

After reset, the default state is GPIO input.

2-8

DSP56824 User’s Manual

Serial Peripheral Interface (SPI) Signals

Table 2-11. Serial Peripheral Interface (SPI0 and SPI1) Signals (Continued)

Signal

State

Signal Name

During

Signal Description

Type

Reset

MOSI1

Input/

Input

SPI1 Master Out/Slave In (MOSI1)— This serial data pin is an out-

output

put from a master device and an input to a slave device. The mas-

ter device places data on the MOSI0 line a half-cycle before the

clock edge that the slave device uses to latch the data. The driver

on this pin can be configured as an open-drain driver by the SPI’s

WOM bit when this pin is configured for SPI operation. When using

Wired-OR mode, the user must provide an external pull-up device.

PC5

Input or

Port C GPIO5 (PC5)— This pin is a GPIO pin called PC5 when the

output

SPI MOSI1 function is not being used.

After reset, the default state is GPIO input.

SCK1

Input/

Input

SPI1 Serial Clock (SCK1)— This bidirectional pin provides a serial

output

bit rate clock for the SPI. This gated clock signal is an input to a

slave device and is generated as an output by a master device.

Slave devices ignore the SCK signal unless the

SS

pin is active

low. In both master and slave SPI devices, data is shifted on one

edge of the SCK signal and is sampled on the opposite edge

where data is stable. The driver on this pin can be configured as an

open-drain driver by the SPI’s WOM bit when this pin is configured

for SPI operation.

PC6

Input or

Port C GPIO 6 (PC6)— This pin is a GPIO pin called PC6 when the

output

SPI SCK1 function is not being used.

After reset, the default state is GPIO input.

Input

Input

SPI1 Slave Select

— This input pin is used to select a slave

SS1

(SS1)

device before a master device can exchange data with the slave

device.

SS

must be low before data transactions and must stay low

for the duration of the transaction. The

SS

line of the master must

be held high.

PC7

Input or

Port C GPIO 7 (PC7)— This pin is a GPIO pin called PC7 when the

output

SPI

SS1

function is not being used.

After reset, the default state is GPIO input.

Signal Descriptions

2-9